
Functional Description
(Continued)
it is made by National Semiconductor, and ‘‘08’’ designates
a 4 Megabit (512K x 8) part.
The code is accessed by applying 12V
g
0.5V to address
pin A9. Addresses A1–A8, A10–A18, and all control pins
are held at V
IL
. Address pin A0 is held at V
IL
for the manu-
facturer’s code, and held at V
IH
for the device code. The
code is read on the eight data pins, O
0
–O
7
. Proper code
access is only guaranteed at 25
§
C
g
5
§
C.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that era-
sure begins to occur when exposed to light with wave-
lengths shorter than approximately 4000 Angstroms (
D
). It
should be noted that sunlight and certain types of fluores-
cent lamps have wavelengths in the 3000
D
–4000
D
range.
The recommended erasure procedure for the EPROM is ex-
posure to short wave ultraviolet light which has a wave-
length of 2537
D
. The integrated dose (i.e., UV intensity X
exposure time) for erasure should be a minimum of
15W-sec/cm
2
.
The EPROM should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure.
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increase as the square of the dis-
tance from the lamp. (If distance is doubled the erasure time
increases by factor of 4.) Lamps lose intensity as they age.
When a lamp is changed, the distance has changed, or the
lamp has aged, the system should be checked to make cer-
tain full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, compo-
nents, and even system designs have been erroneously
suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, I
CC
,
has three segments that are of interest to the system de-
signer: the standby current level, the active current level,
and the transient current peaks that are produced by volt-
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
loading of the device. The associated V
CC
transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1
m
F ceramic
capacitor be used on every device between V
CC
and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7
m
F bulk electrolytic
capacitor should be used between V
CC
and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
Mode Selection
The modes of operation of the NM27P040 are listed in Ta-
ble I. A single 5V power supply is required in the read mode.
All inputs are TTL levels except for V
PP
and A9 for device
signature.
TABLE I. Modes Selection
Pins
CE/PGM
OE
V
PP
V
CC
Outputs
Mode
Read
V
IL
V
IL
X
5.0V
D
OUT
(Note 1)
Output Disable
X
V
IH
X
5.0V
High Z
Standby
V
IH
X
X
5.0V
High Z
Programming
V
IL
V
IH
12.75V
6.25V
D
IN
Program Verify
V
IH
V
IL
12.75V
6.25V
D
OUT
Program Inhibit
V
IH
V
IH
12.75V
6.25V
High Z
Note 1:
X can be V
IL
or V
H
TABLE II. Manufacturer’s Identification Code
Pins
A0
(12)
A9
(26)
O7
(21)
O6
(20)
O5
(19)
O4
(18)
O3
(17)
O2
(15)
O1
(14)
O0
(13)
Hex
Data
Manufacturer Code
V
IL
12V
1
0
0
0
1
1
1
1
8F
Device Code
V
IH
12V
0
0
0
0
1
0
0
0
08
9