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參數(shù)資料
| 型號(hào)： | NM27LV010 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 1,048,576-Bit (128k x 8) Low Voltage EPROM |
| 中文描述： | 1,048,576位（128K的× 8）低電壓存儲(chǔ)器 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 100K |
| 代理商： | NM27LV010 |
8
www.fairchildsemi.com
N
Functional Description
(Continued)
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure
begins to occur when exposed to light with wavelengths shorter
than approximately 4000 Angstroms (). It should be noted that
sunlight and certain types of fluorescent lamps have wavelengths
in the 3000 – 4000 range.
The recommended erasure procedure for the EPROM is expo-
sure to short wave ultraviolet light which has a wavelength of
2537. The integrated dose (i.e., UV intensity x exposure time) for
erasure should be a minimum of 30W-sec/cm
2
.
The EPROM should be placed within 1 inch of the lamp tubes
during erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
An erasure system should be calibrated periodically. The distance
from lamp to device should be maintained at one inch. The erasure
time increases as the square of the distance from the lamp (if
distance is doubled the erasure time increases by factor of 4).
Lamps lose intensity as they age. When a lamp has aged, the
system should be checked to make certain full erasure is occur-
ring. Incomplete erasure will cause symptoms that can be mis-
leading. Programmers, components, and even system designs
have been erroneously suspected when incomplete erasure was
the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful
decoupling of the devices. The supply current, I
, has three
segments that are of interest to the system designer: the standby
current level, the active current level, and the transient current
peaks that are produced by voltage transitions on input pins. The
magnitude of these transient current peaks is dependent on the
output capacitance loading of the device. The associated V
transient voltage peaks can be suppressed by properly selected
decoupling capacitors. It is recommended that at least a 0.1
μ
F
ceramic capacitor be used on every device between V
and
GND. This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7
μ
F bulk electrolytic capacitor
should be used between V
and GND for each eight devices. The
bulk capacitor should be located near where the power supply is
connected to the array. The purpose of the bulk capacitor is to
overcome the voltage drop caused by the inductive effects of the
PC board traces.
Mode Selection
The modes of operation of the NM27LV010 are listed in Table 1. A single 3.3V power supply is required in the read mode. All inputs are
TTL levels except for V
PP
and A9 for device signature.
TABLE 1. Modes Selection
Pins
CE
OE
PGM
V
PP
V
CC
Outputs
Mode
Read
V
IL
V
IL
X
V
CC
3.3V
D
OUT
Output Disable
X (Note 15)
V
IH
X
V
CC
3.3V
High Z
Standby
V
IH
X
X
V
CC
3.3V
High Z
Programming
V
IL
V
IH
V
IL
12.75V
6.25V
D
IN
Program Verify
V
IL
V
IL
V
IH
12.75V
12.75V
D
OUT
Program Inhibit
V
IH
V
IH
X
12.75V
6.25V
High Z
Note 15:
X can be V
IL
or V
IH
.
TABLE 2. Manufacturer’s Identification Code
Pins
A0
(12)
A9
(26)
O7
(21)
O6
(20)
O5
(19)
O4
(18)
O3
(17)
O2
(15)
O1
(14)
O0
(13)
Hex
Data
Manufacturer Code
V
IL
12V
1
0
0
0
1
1
1
1
8F
Device Code
V
IH
12V
1
0
0
0
0
1
1
0
86
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相關(guān)代理商/技術(shù)參數(shù) |
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