參數(shù)資料
型號: NM27C040
廠商: Fairchild Semiconductor Corporation
英文描述: 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
中文描述: 4,194,304位(為512k × 8)高性能CMOS存儲器
文件頁數(shù): 1/11頁
文件大?。?/td> 111K
代理商: NM27C040
1
www.fairchildsemi.com
NM27C040 Rev. C.1
N
NM27C040
4,194,304-Bit (512K x 8) High Performance
CMOS EPROM
General Description
The NM27C040 is a high performance, 4,194,304-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 512K words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature on V
during read operations allows
memory expansions from 1M to 8 Mbits with no printed circuit
board changes.
The NM27C040 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 120ns access time provides high speed
operation with high-performance CPUs. The NM27C040 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The NM27C040 is manufactured using Fairchild’s advanced
CMOS AMG EPROM technology.
Block Diagram
February 1999
Features
I
High performance CMOS
—120, 150ns access time*
I
Simplified upgrade path
—V
PP
is a “Don’t Care” during normal read operation
I
Manufacturer’s identification code
I
JEDEC standard pin configuration
—32-pin PDIP
—32-pin PLCC
—32-pin CERDIP
DS010836-1
AMG is a trademark of WSI, Inc.
1999 Fairchild Semiconductor Corporation
Output Enable,
Chip Enable, and
Program Logic
Y Decoder
X Decoder
.
.
Output
Buffers
Y Gating
4,194,304-Bit
Cell Matrix
Data Outputs O0 - O7
VCC
GND
VPP
OE
CE/PGM
A0 - A18
Address
Inputs
*Note:
New revision meets 70ns. Please check with factory for availability.
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