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參數(shù)資料
| 型號： | NM25W040LZVMT8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| 中文描述： | 512 X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 115K |
| 代理商： | NM25W040LZVMT8 |
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www.fairchildsemi.com
NM25C040 Rev. D.1
N
(
NM25C040
4K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C040 is a 4096-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C040 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C040 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
March 1999
Features
I
2.1 MHz clock rate @ 2.7V to 5.5V
I
4096 bits organized as 512 x 8
I
Multiple chips on the same 3-wire bus with separate chip
select lines
I
Self-timed programming cycle
I
Simultaneous programming of 1 to 4 bytes at a time
I
Status register can be polled during programming to monitor
READY/BUSY
I
Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
I
Block write protect feature to protect against accidental
writes
I
Endurance: 1,000,000 data changes
I
Data retention greater than 40 years
I
Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
DS012401-1
1999 Fairchild Semiconductor Corporation
Instruction
Decoder
Control Logic
and Clock
Generators
High Voltage
Generator
and
Program
Timer
Instruction
Register
Program
Enable
Data In/Out Register
8 Bits
Data Out
Buffer
Non-Volatile
Status Register
Decoder
1 of 512
Address
Counter/
Register
EEPROM Array
4096 Bits
(512 x 8)
Read/Write Amps
CS
HOLD
SCK
V
CC
V
SS
V
PP
WP
SI
SO
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NM25W040LZVMT8X | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| NM25W040LZVN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| NM25W040LZVNX | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| NM25W040M8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| NM25W040M8X | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
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