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參數(shù)資料
| 型號(hào)： | NM24C04UFEN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | NM24C04UFEN |
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www.fairchildsemi.com
NM24C04U/NM24C05U Rev. C.1
N
Device Type
Identifier
Device
Address
1
0
1
0
A2
A1
A0
R/W
(LSB)
NM24C04U/05U
Page
Block Address
DS800008-14
Write Cycle Timing
(Continued)
The NM24C04U/05U device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
both the device and a write operation have been selected, the
NM24C04U/05U will respond with an acknowledge after the
receipt of each subsequent eight bit byte.
In the read mode the NM24C04U/05U slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 5) This
is fixed as 1010 for all EEPROM devices.
Slave Addresses (Figure 5)
Refer to the following table for Slave Addresses string details:
Device
A0 A1 A2
Page
Blocks
Page Block
Addresses
NM24C04U/05U
P
A
A
2
00 01
A: Refers to a hardware configured Device Address pin
P: Refers to an internal PAGE BLOCK memory segment.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Word addressess 0000 through 1111).
Therefore, address bits A0, A1, or A2 (if designated 'P') are used
to access a PAGE BLOCK in conjunction with the Word address
used to access any individual data byte (Word).
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the NM24C04U/05U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the line LOW with an acknowledge signal
and awaits further transmissions.
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PDF描述 |
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| NM24C04UFLEM8 | I2C Serial EEPROM |
| NM24C04UFLEMT8 | I2C Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NM24C04UFLEM8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C04UFLEMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C04UFLEN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| NM24C04UFLM8 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| NM24C04UFLMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
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