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參數(shù)資料
| 型號： | NLSF3T126MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUS BUFFER TRI-ST QUAD 16QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 邏輯類型： | 緩沖器/線路驅(qū)動器，非反相 |
| 元件數(shù)： | 4 |
| 每個元件的位元數(shù)： | 1 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | NLSF3T126MNR2GOSCT |
Semiconductor Components Industries, LLC, 2006
May, 2006 Rev. 5
1
Publication Order Number:
NLSF3T126/D
NLSF3T126
Quad Bus Buffer
with 3State Control Inputs
The NLSF3T126 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves noninverting high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The NLSF3T126 requires the 3state control input (OE) to be set
Low to place the output into high impedance.
The T126 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T126 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
PbFree Package is Available*
L
H
X
H
L
FUNCTION TABLE
Inputs
Output
AOE
L
H
Z
Y
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING DIAGRAM
Device
Package
Shipping
ORDERING INFORMATION
NLSF3T126MNR2
QFN16
3000/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NLSFT126 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
16
NLSF
T126
ALYW
G
1
NLSF3T126MNR2G
QFN16
(PbFree)
3000/Tape & Reel
QFN16
CASE 485G
1
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