參數(shù)資料
型號: NLAS3158MNR2G
廠商: ON SEMICONDUCTOR
元件分類: 多路復(fù)用及模擬開關(guān)
英文描述: Low Voltage Dual SPDT Analog Switch Dual 2:1 Multiplexer
中文描述: DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, DSO12
封裝: LEAD FREE, QFN-12
文件頁數(shù): 1/12頁
文件大?。?/td> 88K
代理商: NLAS3158MNR2G
Semiconductor Components Industries, LLC, 2005
March, 2005 Rev. 0
1
Publication Order Number:
NLAS3158/D
NLAS3158
Low Voltage Dual SPDT
Analog Switch Dual 2:1
Multiplexer
The NLAS3158 is an advanced CMOS analog switch fabricated
with silicon gate CMOS technology. It achieves very low
propagation delay and RDS
ON
resistances while maintaining CMOS
low power dissipation. Analog and digital voltages that may vary
across the full powersupply range (from V
CC
to GND). This device
is a drop in replacement for the PI5A3158.
The select pin has overvoltage protection that allows voltages
above V
CC,
up to 7.0 V to be present on the pin without damage or
disruption of operation of the part, regardless of the
operating voltage.
Features
High Speed: t
PD
= 1.0 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 1.0 A (Max) at T
A
= 25
°
C
Standard CMOS Logic Levels
High Bandwidth, Improved Linearity
Low RDS
ON
: 8 Max at 3 V
Break Before Make Circuitry, Prevents Inadvertent Shorts
This is a PbFree Device
Typical Applications
Switches Standard NTSC/PAL Video, Audio, SPDIF and HDTV
May be used for Clock Switching, Data MUX’ing, etc.
Can Switch Balanced Signal Pairs, e.g. LVDS
200 Mb/s
Important Information
Latchup Performance Exceeds 300 mA
Pin for Pin Drop in for PI5A3158
TDFN Package, 3x1 mm
ESD Performance: Human Body Model;
2000 V;
Machine Model;
200 V
Extended Automotive Temperature Range 55
°
C to +125
°
C
(See Appendix A)
DFN12
MN SUFFIX
CASE 485AG
http://onsemi.com
MARKING DIAGRAM
AS
C
= Specific Device Code
= Date Code
L
H
FUNCTION TABLE
Select Input
Function
B0 Connected to A
B1 Connected to A
1
12
1
ASC
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
Figure 1. Pinout
(Top View)
S
1
A
0
GND
A
1
0
B
0
1
2
3
12
10
V
CC
11
4
5
6
9
7
8
1
B
0
GND
1
B
1
V
CC
S
0
0
B
1
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