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參數(shù)資料
| 型號(hào)： | NL37WZ14USG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INVERT TRPL SCHMT TRIG US8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 37WZ |
| 邏輯類型： | 逆變器，緩沖器 |
| 電路數(shù)： | 3 |
| 輸入數(shù)： | 1 |
| 特點(diǎn)： | 施密特觸發(fā)器 |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 32mA，32mA |
| 邏輯電平 - 低： | 0.4 V ~ 1.2 V |
| 邏輯電平 - 高： | 1.8 V ~ 3.6 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 4.9ns @ 5V，50pF |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | US8 |
| 封裝/外殼： | 8-VFSOP（0.091"，2.30mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NL37WZ14USGOSDKR |
Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 8
1
Publication Order Number:
NL37WZ14/D
NL37WZ14
Triple Schmitt-Trigger
Inverter
The NL37WZ14 is a high performance triple inverter with
SchmittTrigger inputs operating from a 1.65 to 5.5 V supply.
Pin configuration and function are the same as the NL37WZ04, but
the inputs have hysteresis, and with its Schmitt trigger function, the
NL37WZ14 can be used as a line receiver which will receive slow
input signals. The NL37WZ14 is capable of transforming slowly
changing input signals into sharply defined, jitterfree output signals.
In addition, it has a greater noise margin than conventional inverters.
The NL37WZ14 has hysteresis between the positivegoing and the
negativegoing input thresholds (typically 1.0 V) which is determined
internally by transistor ratios and is essentially insensitive to
temperature and supply voltage variations.
Features
Designed for 1.65 V to 5.5 V VCC Operation
Over Voltage Tolerant Inputs and Outputs
LVTTL Compatible Interface Capability with 5 V TTL Logic
with VCC = 3 V
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Current Drive Capability is 24 mA at the Outputs
Chip Complexity: FET = 94
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
IN A2
OUT Y2
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
OUT Y1
IN A1
OUT Y3
IN A3
VCC
IN A1
OUT Y3
GND
IN A2
OUT Y2
1
2
3
8
7
6
IN A3
OUT Y1
45
1
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
PIN ASSIGNMENT
1
2
3IN A2
IN A1
GND
4
5
OUT Y3
OUT Y1
6
FUNCTION TABLE
L
H
A Input
Y Output
H
L
7
8
VCC
IN A3
OUT Y2
US8
US SUFFIX
CASE 493
8
1
http://onsemi.com
1
8
LA
= Device Code
M
= Date Code*
G
= PbFree Package
LA M G
G
*Date Code orientation may vary depending upon
manufacturing location.
(Note: Microdot may be in either location)
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相關(guān)代理商/技術(shù)參數(shù) |
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| NL37WZ14USG-CUT TAPE | 制造商:ON 功能描述:NL37WZ14 Series 1.65 to 5.5 V Triple Inverter Schmitt - US-8 |
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| NL37WZ16/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Triple Buffer |
| NL37WZ16_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Triple Buffer |
| NL37WZ16_12 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Triple Buffer |
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