參數(shù)資料
型號: NJW1180FP1
廠商: New Japan Radio Co., Ltd.
英文描述: Audio Processor with SRS WOW
中文描述: 音頻處理器采用SRS WOW
文件頁數(shù): 5/15頁
文件大?。?/td> 344K
代理商: NJW1180FP1
NJW1180
– 5 –
I
I
2
C BUS CHARACTERISTICS (SDA, SCL)
I
2
C BUS Load Conditions: Pull up resistance 4k
(Connected to +5V), Load capacitance 200pF (Connected to GND)
STANDARD MODE
FAST MODE
PARAMETER
SYM
BOL
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNIT
Low Level Input Voltage
V
IL
V
IH
V
hys
V
OL
0.0
-
1.5
0.0
-
1.5
V
High Level Input Voltage
2.7
-
5.0
2.7
-
5.0
V
Hysteresis of Schmitt trigger inputs
-
-
-
0.25
-
-
V
LOW level output voltage (3mA at SDA pin)
0
-
0.4
0
-
0.4
V
Output fall time from V
IHmin
to V
ILmax
with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed by the input
filter
Input current each I/O pin with an input voltage between
0.1V
DD
and 0.9V
DDmax
Capacitance for each I/O pin
t
of
-
-
250
20
+0.1C
b
-
250
ns
t
SP
-
-
-
0
-
50
ns
I
i
-10
-
10
-10
-
10
μA
C
i
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
-
-
10
-
-
10
pF
SCL clock frequency
-
-
100
-
-
400
kHz
Hold time (repeated) START condition.
4.0
-
-
0.6
-
-
μs
LOW period of the SCL clock
4.7
-
-
1.3
-
-
μs
HIGH period of the SCL clock
4.0
-
-
0.6
-
-
μs
Set-up time for a repeated START condition
4.7
-
-
0.6
-
-
μs
Data hold time
0
-
3.45
0
-
0.9
μs
Data set-up time
250
-
-
100
-
-
ns
Rise time of both SDA and SCL signals
-
-
1000
-
-
300
ns
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Noise margin at the LOW level
Noise margin at the HIGH level
-
-
-
300
-
-
-
-
300
-
ns
μs
4.0
0.6
t
BUF
4.7
-
-
1.3
-
-
μs
C
b
V
nL
V
nH
-
-
-
-
400
-
-
C
b
; total capacitance of one bus line in pF.
-
-
-
-
400
-
-
pF
V
V
0.5
1
0.5
1
SDA
SCL
t
f
t
HD:STA
t
LOW
t
r
t
HD:DAT
t
HIGH
t
f
t
SU:DAT
S
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
Sr
t
r
t
BUF
P
S
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