參數(shù)資料
型號： NJW1146
廠商： New Japan Radio Co., Ltd.
英文描述： Audio Processor with BBE
中文描述： BBE的音頻處理器
文件頁數(shù)： 4/21頁
文件大?。?/td> 243K
代理商： NJW1146
NJW1146
– 4 –
PRELIMINARY
N
AGC CHARACTERISTICS
(Ta=25
°
C, V
+
=9V, R
L
=47k
MODE ; VOL=0dB, BAL=0dB, AGC=ON, BBE=OFF, Tone=0dB, eala=By-Pass)
PARAMETER
SYMBOL
AGC Boost
G
AGCBST
AGC Flat 1
G
AGCFLT1
AGC Flat 2
G
AGCFLT2
AGC Flat 3
G
AGCFLT3
AGC Flat 4
G
AGCFLT4
AGC Cut
G
AGCCUT
TEST CONDITION
Vin=50mVrms, f=1kHz
Vin=300mVrms, f=1kHz
Vin=400mVrms, f=1kHz
Vin=500mVrms, f=1kHz
Vin=600mVrms, f=1kHz
Vin=2Vrms, f=1kHz
MIN.
1.5
-2.5
-2.5
-2.5
-2.5
-14
TYP.
3.5
0.0
0.0
0.0
0.0
-10
MAX.
5.5
2.5
2.5
2.5
2.5
-6.0
UNIT
dB
dB
dB
dB
dB
dB
N
BBE CHARACTERISTICS
(Ta=25
°
C, V
+
=9V, R
L
=47k
, Vin=100mVrms/1kHz
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, Tone=0dB, eala=By-Pass)
PARAMETER
SYMBOL
Low Boost Gain
G
BBELOW
High Boost Gain
G
BBEHIGH
TEST CONDITION
BBE-LOW =+15dB, f=50Hz
BBE-HIGH =+15dB, f=10kHz
MIN.
12.5
12.5
TYP.
15
15
MAX.
17.5
17.5
UNIT
dB
dB
N
eala CHARACTERISTICS
(Ta=25
°
C, V
+
=9V, R
L
=47k
, Vin=100mVrms/1kHz
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, BBE=0dB, Tone=0dB)
PARAMETER
SYMBOL
Simulated Stereo A
G
SIMA
Simulated Stereo B
G
SIMB
Surround 3D1
G
3D1
Surround 3D2
G
3D2
Surround 3D3
G
3D3
Surround 3D4
G
3D4
I
I
2
C BUS CHARACTERISTICS (SDA, SCL)
I
2
C BUS Load Conditions: Pull up resistance 4k
(Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
TEST CONDITION
MIN.
1.0
1.0
5.5
-2.0
0.5
3.5
TYP.
3.0
3.0
7.5
0.0
2.5
5.5
MAX.
5.0
5.0
9.5
2.0
4.5
7.5
UNIT
dB
dB
dB
dB
dB
dB
LIN+RIN
→
OUTa, f=1KHz, SIM
LIN+RIN
→
OUTb, f=1KHz, SIM
LIN
→
OUTa, f=100Hz, SR2
LIN
→
OUTa, f=10KHz, SR2
LIN
→
OUTb, f=100Hz, SR2
LIN
→
OUTa, f=100Hz, SR1
SYMBOL
MIN.
TYP.
MAX.
UNIT
High Level Input Voltage
V
IH
V
IL
I
IH
I
IL
V
OL
I
OL
f
SCL
t
BUF
t
HD:STA
t
LOW
T
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
3.0
-
5.0
V
Low Level Input Voltage
0
-
1.5
V
High Level Input Current
-
-
10
μ
A
Low Level Input Current
-
-
10
μ
A
Low Level Output Voltage (3mA at SDA pin)
0
-
0.4
V
Maximum Output Current
-3.0
-
-
mA
Maximum Clock Frequency
0
-
100
kHz
Data Change Minimum Waiting Time
4.7
-
-
μ
s
Data Transfer Start Minimum Waiting Time
4.0
-
-
μ
s
Low Level Clock Pulse Width
4.7
-
-
μ
s
High Level Clock Pulse Width
4.0
-
-
μ
s
Minimum Start Preparation Waiting Time
4.7
-
-
μ
s
Minimum Data Hold Time
5.0
-
-
μ
s
Minimum Data Preparation Time
250
-
-
ns
Rise Time
-
-
1.0
μ
s
Fall Time
-
-
300
ns
Minimum Stop Preparation Waiting Time
4.7
-
-
μ
s
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