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參數(shù)資料
| 型號(hào)： | NJU26175 |
| 廠商： | New Japan Radio Co., Ltd. |
| 英文描述： | NJU26100 Series Hardware Specification |
| 中文描述： | NJU26100系列硬件規(guī)格 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 270K |
| 代理商： | NJU26175 |
Ver.2005-02-24
NJU26100 Series
- 5 -
2. Clock and Reset
The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The
XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator.
When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the
maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum
voltage-level of XI pin equals to V
DD
.
To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series.
To select I
2
C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin
(SEL1 pin)=”Low”, I
2
C bus is selected. When GPIO0 pin (SEL1 pin)=”High”, 4-Wire serial bus is selected. The level
of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to “High”.
After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept
Low-level more than t
RESETb
period.
Fig. 2- 1 Reset Timing
Table 2- 1 Reset Time
Symbol
t
RESETb
Notice :
Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts.
NJRC would not take the responsibility on the external parts of clock generating.
Time
≥
1
μ
s
OSC unstable
OSC stable
XI
V
DD
RESETb
t
RESETb
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