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參數(shù)資料
| 型號： | NE521NG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR/SENSE AMP 14-DIP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 差分 |
| 元件數(shù)： | 2 |
| 輸出類型： | TTL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 7.5mV @ ±4.75V |
| 電流 - 輸入偏壓（最小值）： | 20µA @ ±5.25V |
| 電流 - 靜態(tài)（最大值）： | 35mA |
| 傳輸延遲（最大）： | 12ns |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 安裝類型： | 通孔 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1131 (CN2011-ZH PDF) |
| 其它名稱： | NE521NG-ND NE521NGOS |
Semiconductor Components Industries, LLC, 2006
October, 2006 Rev. 4
1
Publication Order Number:
NE521/D
NE521
HighSpeed
DualDifferential
Comparator/Sense Amp
Features
TTL-Compatible Strobes and Outputs
Large Common-Mode Input Voltage Range
Operates from Standard Supply Voltages
PbFree Packages are Available
Applications
MOS Memory Sense Amp
A-to-D Conversion
High-Speed Line Receiver
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage
Positive
Negative
V+
V
+7.0
7.0
V
Differential Input Voltage
VIDR
"6.0
V
Input Voltage
Common Mode
Strobe/Gate
VIN
"5.0
+5.25
V
Maximum Power Dissipation (Note 1)
TA = 25°C (StillAir)
N Package
D Package
PD
1420
1040
mW
Thermal Resistance, JunctiontoAmbient
N Package
D Package
RqJA
100
145
°C/W
Operating Temperature Range
TA
0 to 70
°C
Storage Temperature Range
Tstg
65 to +150
°C
Operating Junction Temperature
TJ
150
°C
Lead Soldering Temperature (10 sec max)
Tsld
+230
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
RecommendedOperating Conditions may affect device reliability.
1. Derate above 25°C at the following rates:
N package at 10 mW/°C
D package at 6.9 mW/°C.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
PIN CONNECTIONS
SOIC14
D SUFFIX
CASE 751A
INPUT 1A
INPUT 1B
NC
V+
V
INPUT 2A
INPUT 2B
OUTPUT 1Y
STROBE 1G
GROUND
NC
OUTPUT 2Y
STROBE 2G
D, N Packages
STROBE S
1
2
3
4
5
6
7
14
13
12
11
10
9
8
(Top View)
1
PDIP14
N SUFFIX
CASE 646
1
NE521G
AWLYWW
1
MARKING
DIAGRAMS
NE521N
AWLYYWWG
A
= Assembly Location
WL
= Wafer Lot
Y, YY = Year
WW = Work Week
G
= PbFree Package
1
14
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