參數(shù)資料
型號(hào): NCV8509PDW25G
廠商: ON SEMICONDUCTOR
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Sequenced Linear Dual−Voltage Regulator
中文描述: DUAL OUTPUT, FIXED POSITIVE REGULATOR, PDSO16
封裝: LEAD FREE, SOIC-16
文件頁(yè)數(shù): 16/19頁(yè)
文件大?。?/td> 198K
代理商: NCV8509PDW25G
NCV8509 Series
http://onsemi.com
16
V
OUT1
V
OUT2
Short On
V
OUT1
Short On
V
OUT2
10
μ
s
10
μ
s
Fast SLEW Rate >> Soft Start
Figure 52. Fault Response. Note the High SLEW Rate Coming Out of Fault Conditions.
Soft Start Only Applies to a Power Up Sequence.
Fast SLEW Rate >> Soft Start
Decay Time Dependent
on External Load
Decay Time Dependent
on External Load
Disable Time
Disable Time
Slew Rate Control
Figure 53 shows the circuitry associated with Slew Rate
Control. The diagram highlights the control of one output for
simplicity. V
OUT1
and V
OUT2
are both controlled on the IC.
The slew rate capacitor (C
SLEW
) is charged with an
onchip current source runing at 6.0 A (typ.). Charging a
capacitor with a current source creates a linear voltage ramp
as shown in Figure 54.
The lowest voltage to the positive terminals of the
comparator (Error Amp) dominates the output voltage
(V
OUT
). Consequently, when C
SLEW
is fully discharged on
power up, it is the dominant factor on the positive terminal
and disables the output. The output (V
OUT
) follows the
linear ramp on the SLEW pin (after being gained up with R1
and R2) until V
BG
becomes the dominant voltage. This
occurs when SLEW = V
BG
+ V
D1
or approximately 1.8 V.
R1
+
+
V
OUT
R2
Error Amp
SLEW
C
SLEW
6.0
μ
A
Internal
Voltage
Rail
3.8 V
D2
V
IN1
D1
V
BG
Figure 53. Slew Control Circuitry
Slew time can be calculated using the standard capacitor
equation.
Cdt, t
Using a 33 nF capacitor, the slew time is:
(33 nF)(1.8 V)
6 A
The corresponding slew rate for this is 1.8 V/9.9 ms =
182 V/s ON THE SLEW PIN.
To calculate the slew rate on outputs, you must multiply
by the gain set up by R1 and R2.
VOUT
1.28 V
For a 5 V output, the gain would be:
5 V
1.28 V
assuming V
BG
= 1.28 V.
The resultant slew rate on the output is the slew rate on the
SLEW pin multiplied by the gain, or:
(182 V s)
(3.9 V V)
I
C( V)
I
t
9.9 ms
Av
Av
3.9 V V
710 V s
Outputs in Regulation
Figure 54.
Time (ms)
S
3.8
1.8
t
SLEW
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