參數(shù)資料
型號(hào): NCV8141D2T
廠商: ON SEMICONDUCTOR
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: 5.0 V, 500 mA Linear Regulator with ENABLE, RESET, and Watchdog
中文描述: 5 V FIXED POSITIVE REGULATOR, PSSO7
封裝: D2PAK-7
文件頁數(shù): 6/12頁
文件大?。?/td> 89K
代理商: NCV8141D2T
NCV8141
http://onsemi.com
6
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
Figure 5. Typical Circuit Waveforms for Output
Stage Protection
I
O
Load
Dump
V
IN
V
OUT
Thermal
Shutdown
Short
Circuit
> 30 V
Should the junction temperature of the power device
exceed 180
°
C (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
REGULATOR CONTROL FUNCTIONS
The NCV8141 differs from all other linear regulators in its
unique combination of control features.
Watchdog and ENABLE Function
V
OUT
is controlled by the logic functions ENABLE and
Watchdog (Table 1).
Table 1. V
OUT
as a Function of ENABLE and Watchdog
V
OUT
(V)
WDI
ENABLE
Slow
Normal
Fast
High
Low
H
5
5
5
5
5
L
0
5
0
0
0
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V
OUT
will be at 5.0 V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and the
IC goes into SLEEP mode. Only the ENABLE circuitry in
the IC remains powered up, drawing a quiescent current of
less than 50 A.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
RESET lead (Figure 6) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of C
DELAY
. The limits
are determined according to the following equations for the
NCV8141:
105)CDELAYor
tWDI
(1.3
fWDI
(7.69
106)CDELAY1
The capacitor C
DELAY
also determines the frequency of
the RESET signal and the POWERONRESET (POR)
delay period.
RESET Function
The RESET function is activated when the Watchdog
signal is outside of its preset window (Figure 6), when the
regulator is in its power up state (Figure 7) or when V
OUT
drops below V
OUT
4.5% for more than 2.0 s (Figure 8)
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the RESET lead (Figure 6) until the
correct Watchdog input signal reappears at the lead. The
duration of the RESET pulse is determined by C
DELAY
according to the following equation:
tWDI(RESET)
(1.0
104)CDELAY
RESET CIRCUIT WAVEFORMS WITH DELAYS
INDICATED
If an undervoltage condition exists, the voltage on the
RESET lead goes low and the delay capacitor, C
DELAY
, is
discharged. RESET remains low until output is in
regulation, the voltage on C
DELAY
exceeds the upper
switching threshold and the Watchdog input signal is within
its set window limits (Figures 7 and 8). The delay after the
output is in regulation is:
tPOR(typ)
(4.75
105)CDELAY
The RESET delay circuit is also programmed with the
external cap C
DELAY
.
The output of the reset circuit is an open collector NPN.
RESET is operational down to V
OUT
= 1.0 V. Both RESET
and its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
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