
NCV7702B
http://onsemi.com
7
Functional Description
The NCV7702B is arranged as four halfbridge drivers in
two independent channels. Each channel can be operated as
a fullbridge or halfbridge to drive multiple load
configurations. Separate ENable inputs are used to control
which channel is active. Each ENable input has a nominal
50 k internal pulldown resistor to ensure that the outputs
remain off during powerup. The four IN
X
control inputs
address each halfbridge output, and each output follows the
state of its input. When IN
X
is at logic one, OUT
X
is sourcing
current from the VB supply; when IN
X
is at logic zero,
OUT
X
is sinking current to the PGND return.
HalfBridge Drivers
The halfbridge drivers of each OUT
X
are comprised of
an NPN Darlington driver on the lowside and a compound
PNPNPN driver on the highside. Each halfbridge driver
is capable of 1 A (min) peak current and is overcurrent
protected against load and system faults. Cross conduction
currents within each halfbridge are suppressed by the use
of a deadband timer. Each IN
X
input contains an
independent deadband timer that is activated on either
edge of the input transition.
Overcurrent detection circuitry is provided in both the
lowside and highside drivers of each halfbridge output.
When activated, the overcurrent detectors trigger an internal
timer which causes both halfbridge drivers in the same
channel to be modulated at 4% (Typ.) duty cycle. The timer
also activates the channel’s STATUS output, causing it to be
similarly modulated (see Figure 5.) Upon removal of the
fault condition, the channel automatically resumes
operation in its previously programmed mode and its
STATUS output returns to a nofault state.
Recirculation diodes at each OUT
X
clamp load transients
to either VB or PGND and help contain switching currents
within each load loop.
Overcurrent Duty Cycle Timer
A single timer for overcurrent duty cycle is common to
both channels. The timer is triggered when a halfbridge in
either channel has detected an overcurrent fault. An external
capacitor connected to the NCV7702B’s C
T
pin is used to
program the period of the timer, and the ratio of two
internally fixed currents programs the timer’s duty cycle.
The capacitor voltage is normally kept at zero by discharge
current I
DCH
. Upon detection of overcurrent, charging
current I
CHG
is switched on and the C
T
capacitor begins
charging from zero towards the timer’s upper threshold
(V
DH.
) When the capacitor voltage crosses V
DH
the faulted
channel’s outputs are switched off and the channel’s
STATUS output is switched from V
SH
to V
SL
(see Figure 5.)
The charging current is switched off, and the capacitor
voltage decreases toward the timer’s lower (V
DL
) threshold.
Upon crossing the lower threshold, the channel’s outputs are
switched on and the channel’s STATUS output returns to its
V
SH
voltage. This behavior continues until the fault
condition is resolved. If the fault condition is resolved
before V
DH
is reached, the timer is reset and no modulation
of the previously faulted channel’s halfbridge or STATUS
outputs occurs.
After the timer’s initial charge cycle, the output off time
is:
t
OFF
= C
T
(V
CH
V
Dc
)/ I
DCH
.
The output on time is:
t
ON
= C
T
(V
CH
V
Dc
)/ I
CHG
.
The timer period is:
T = t
OFF
+ t
ON
.
The value of the C
T
capacitor is required to be in the range
of 470 to 1500 pF. Values below 470 pF may cause timer
misoperation due to internal delays, while values above
1500 pF may cause excessive power dissipation.
Connecting the C
T
pin to ground will prevent operation of
the current limit function.
Overvoltage and Overtemperature Protection
Overvoltage detection circuitry is intended to allow
limited operation of the NCV7702B during doublebattery
conditions. Detection is via the VB1 pin and causes both
channels of the IC to be switched off when the detection
threshold is exceeded. Hysteresis is provided to improve
noise immunity of the overvoltage function.
Overtemperature detection circuitry monitors the
junction temperature internal to the IC and is intended to
ensure reliability by preventing excessive power
dissipation. The detection circuitry is centrally located on
the IC and causes both channels of the IC to be switched off
when the detection threshold is exceeded. Hysteresis is
provided to improve noise immunity of the overtemperature
function.
Both STATUS outputs are switched to the V
SL
state
during either overvoltage or overtemperature faults. Normal
operation of the IC is resumed automatically upon resolution
the fault, and the STATUS outputs return to the V
SH
State.