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參數(shù)資料
| 型號： | NCV7001DWR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SENSOR QUAD 24SOIC |
| 產(chǎn)品變化通告： | Product Obsolescence 19/Dec/2008 |
| 標準包裝： | 1,000 |
| 類型： | 可變磁阻 |
| 輸入類型： | * |
| 輸出類型： | * |
| 接口： | 差分 |
| 電流 - 電源： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | NCV7001DWR2GOS |
NCV7001
http://onsemi.com
5
PIN DESCRIPTION
Pin No.
Symbol
Description
1
RDLY
Determines the low voltage reset delay and watchdog enable and disable delay.
2
NTEST
Low = test, high = normal operation.
3
INN1
Minus input to channel 1 comparator.
4
INP1
Plus input to channel 1 comparator.
5
INN2
Minus input to channel 2 comparator.
6
INP2
Plus input to channel 2 comparator.
7
INP3
Plus input to channel 3 comparator.
8
INN3
Minus input to channel 3 comparator.
9
INP4
Plus input to channel 4 comparator.
10
INN4
Minus input to channel 4 comparator.
11
THOLD
Variable threshold adjustment.
12
GND
Ground.
13
NOUT4
Inverted output of comparator 4.
14
NOUT3
Inverted output of comparator 3.
15
WDLY
Determines watchdog timing.
16
OLE
Disables outputs. High = normal operation. Low = forces all outputs and comparators high.
17
WD1
Watchdog input.
18
VCC
5.0 V input to IC.
19
WD2
Watchdog input.
20
NLVI
Reset output (in reset when low).
21
LVI
Reset output (in reset when high).
22
WDO
Watchdog output (low for valid watchdog signal).
23
NOUT2
Inverted output of comparator 2.
24
NOUT1
Inverted output of comparator 1.
Table 1. Wheel Speed Output Functionality
Sensor
NTEST
OLE
NOUTx
OPEN
L
H
OPEN
L
H
L
OPEN
H
L
H
OPEN
H
X
NORMAL
L
H
NORMAL
L
H
NORMAL
H
L
H
NORMAL
H
X
X = Do not care (dependent on presence of sensor signal).
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