參數(shù)資料
型號(hào): NCV4279
廠商: ON SEMICONDUCTOR
英文描述: 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output(帶有延遲,可調(diào)復(fù)位和檢測輸出功能的5.0V,微功率150mA LDO線性穩(wěn)壓器)
中文描述: 5.0V的微一百五十毫安LDO線性穩(wěn)壓器的延遲,可調(diào)復(fù)位和檢測輸出(帶有延遲,可調(diào)復(fù)位和檢測輸出功能的5.0V,150mA的微功率LDO的線性穩(wěn)壓器)
文件頁數(shù): 10/14頁
文件大小: 114K
代理商: NCV4279
NCV4279
http://onsemi.com
10
APPLICATION DESCRIPTION
OUTPUT REGULATOR
The output is controlled by a precision trimmed reference.
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage V
Q
increases above the reset threshold voltage V
RT
, the delay
timer D is started. When the voltage on the delay timer V
D
passes V
UD
, the reset signal RO goes high. A discharge of
the delay timer V
D
is started when V
Q
drops and stays below
the reset threshold voltage V
RT
. When the voltage of the
delay timer V
D
drops below the lower threshold voltage V
LD
the reset output voltage V
RO
is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for V
Q
as low as 1.0 V.
RESET ADJUST (R
ADJ
)
The reset threshold V
RT
can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 18. The resistor divider keeps the voltage
above the V
RADJ,TH
(typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
VRT
VRADJ,TH
(RADJ1
RADJ2) RADJ2
(eq. 1)
If the reset adjust option is not needed, the R
ADJ
pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor C
D
) on the reset output lead RO. The delay lead D
provides charge current I
D
(typically 6.5 A) to the external
delay capacitor C
D
during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (V
RT
, reset
threshold voltage) has been violated. When the
delay capacitor discharges to V
LD
, the reset signal
RO pulls low.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor C
D
and the
charge current I
D
. The time is measured by the delay
capacitor voltage charging from the low level of V
DSAT
to
the higher level V
UD
. The time delay follows the equation:
td
[CD(VUD
VDSAT)] ID
(eq. 2)
Example:
Using C
D
= 100 nF.
Use the typical value for V
DSAT
= 0.1 V.
Use the typical value for V
UD
= 1.8 V.
Use the typical value for Delay Charge Current I
D
= 6.5 A.
td
[100 nF(1.8
0.1 V)] 6.5 A
26.2 ms
(eq. 3)
Q
GND
I
R
ADJ
NCV4279
C
Q
**
10 F
RO
0.1 F
M
D
C
D
V
BAT
V
DD
SO
Figure 18. Application Diagram
SI
I/O
I/O
R
ADJ2
R
ADJ1
R
SI1
R
SI2
C
I
*
*C
I
required if regulator is located far from the power supply filter.
** C
Q
required for Stability. Cap must operate at minimum temperature expected.
R
SO
R
RO
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