參數(shù)資料
型號(hào): NCV4274A
廠商: ON SEMICONDUCTOR
英文描述: 400 mA 2% and 4%Voltage Regulator Family(400mA 2%和4%穩(wěn)壓器系列)
中文描述: 400毫安2%和4%穩(wěn)壓器系列(400mA的2%和4%,穩(wěn)壓器系列)
文件頁數(shù): 2/16頁
文件大?。?/td> 127K
代理商: NCV4274A
NCV4274, NCV4274A
http://onsemi.com
2
Figure 1. Block Diagram
-
+
Bandgap
Refernece
Thermal
Shutdown
Current Limit and
Saturation Sense
GND
Q
I
Pin Definitions and Functions
Pin No.
Symbol
Function
1
I
Input; Bypass directly at the IC a ceramic capacitor to GND.
2,4
GND
Ground
3
Q
Output; Bypass with a capacitor to GND.
1. DPAK 3LD package code 6025
2. D2PAK 3LD package code 6083
ABSOLUTE MAXIMUM RATINGS
Pin Symbol, Parameter
Symbol
Condition
Min
Max
Unit
I
, Input-to-Regulator
Voltage
V
I
-42
45
V
Current
I
I
Internally
Limited
Internally
Limited
I
, Input peak Transient Voltage to Regulator with Respect
to GND
V
I
60
V
Q,
Regulated Output
Voltage
V
Q
V
Q
=
V
I
-1.0
40
V
Current
I
Q
Internally
Limited
Internally
Limited
GND,
Ground Current
I
GND
-
100
mA
Junction Temperature
Storage Temperature
T
J
T
Stg
-
-50
150
150
°
C
°
C
ESD Capability, Human Body Model
ESD
HB
4
kV
ESD Capability, Machine Model
ESD
MM
200
V
ESD Capability, Charged Device Model
ESD
CDM
1
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC-Q100-002 (EIA/JESD22-A114)
ESD MM tested per AEC-Q100-003 (EIA/JESD22-A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
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