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參數(shù)資料
| 型號： | NCT214MT3R2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC10 |
| 封裝： | 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, WQFN-10 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 269K |
| 代理商： | NCT214MT3R2G |
NCT214
http://onsemi.com
13
or read from, the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the acknowledge bit. All other devices
on the bus remain idle while the selected device
waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave
device. If the R/W bit is a 1, the master reads from
the slave device.
2. Data is sent over the serial bus in a sequence of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
high period, since a lowtohigh transition when
the clock is high can be interpreted as a stop
signal. The number of data bytes that can be
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as no acknowledge. The master
takes the data line low during the low period
before the tenth clock pulse, then high during the
tenth clock pulse to assert a stop condition.
Any number of bytes of data are transferable over
the serial bus in one operation, but it is not
possible to mix read and write in one operation
because the type of operation is determined at the
beginning and cannot subsequently be changed
without starting a new operation. For the NCT214,
write operations contain either one or two bytes,
while read operations contain one byte.
To write data to one of the device data registers, or to read
data from it, the address pointer register must be set so that
the correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
This procedure is illustrated in Figure 15. The device
address is sent over the bus followed by R/W set to 0. This
is followed by two data bytes. The first data byte is the
address of the internal data register to be written to, which
is stored in the address pointer register. The second data byte
is the data to be written to the internal data register.
Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
Figure 16. Writing to the Address Pointer Register Only
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
ACK. BY
NCT1008
STOP BY
MASTER
SDATA (CONTINUED)
SCLK (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
NCT214
SDATA
SCLK
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
A6
A5
A4
A3
A2
A1
A0
R/W
ACK. BY
1
9
1
9
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
NCT214
SDATA
SCLK
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
A6
A5
A4
A3
A2
A1
A0
R/W
ACK. BY
1
9
STOP BY
MASTER
NCT214
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