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參數(shù)資料
| 型號： | NCP5211DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Low Voltage Synchronous Buck Controller |
| 中文描述： | 1 A SWITCHING CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 132K |
| 代理商： | NCP5211DR2G |
NCP5211
http://onsemi.com
11
V
FFB
Feedback Selection
To take full advantage of the V
2
control scheme, a small
amount of output ripple must be fed back to the V
FFB
pin,
typically 50 mV. For most application, this requirement is
simple to achieve and the V
FFB
can be connected directly to
the V
FB
pin. There are some application that have to meet
stringent load transient requirements. One of the key factor
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. This situation could result in increase noise
sensitivity and a potential for loop instability. In applications
where the output ripple is not sufficient, the performance of
the NCP5211 can be improved by adding a fixed amount
external ramp compensation to the V
FFB
pin. Refer to Figure
7, the amount of ramp at the V
FFB
pin depends on the switch
node Voltage, Feedback Voltage, R1 and C2.
Vramp
(Vsw
VFB)
ton (R1
C2)
where:
Vramp = amount of ramp needed;
Vsw = switch note voltage;
V
FB
= voltage feedback, 1 V;
ton = switch ontime.
To minimize the lost in efficiency R1 resistance should be
large, typically 100 k or larger. With R1 chosen, C2 can be
determined by the following;
C2
(Vsw
VFB)
ton (R1
Vramp)
C1 is used as a bypass capacitor and its value should be
equal to or greater than C2.
Figure 7. Small RC Filter Providing the Proper Voltage
Ramp at the Beginning of Each OnTime Cycle
Vsw
R2
1.0 k
V
FFB
V
FB
R1
C1
C2
Maximum Frequency Operation
The minimum pulse width may limit the maximum
operating frequency. The duty factor, given by the output/input
voltage ratio, multiplied by the period determines the pulse
width during normal operation. This pulse width must be
greater than 200 ns, or duty cycle jitter could become
excessive. For low pulse widths below 300 ns, external slope
compensation should be added to the V
FFB
pin to increase the
PWM ramp signal and improve stability. 50 mV of added ramp
at the V
FFB
pin is typically enough.
Current Sense Component Selection
The current limit threshold is set by sensing a 60 mV
voltage differential between the IS+ and IS pins. Referring
to Figure 8, the time constant of the R2,C1 filter should be
set larger than the L/R1 time constant under worst case
tolerances, to prevent overshoot in the sensed voltage and
tripping the current limit too low. Resistor R3 of value equal
to R2 is added for bias current cancellation. R2 and R3
should not be made too large, to reduce errors from bias
current offsets. For typical L/R time constants, a 0.1 F
capacitor for C1 will allow R2 to be between 1.0 k and 10 k .
The current limit without R4 and R5, which are optional, is
given by 60 mV/R1, where R1 is the internal resistance of the
inductor, obtained from the manufacturer. The addition of R5
can be used to decrease the current limit to a value given by:
ILIM
(60 mV
(VOUT
R3 (R3
R5)) R1
where V
OUT
is the output voltage.
Similiarly, omitting R5 and adding R4 will increase the
current limit to a value given by:
ILIM
60 mV R1
(1
R2 R4)
Essentially, R4 or R5 are used to increase or decrease the
inductor voltage drop which corresponds to 60 mV at the IS+
and IS pins.
Figure 8. Current Limit
R5
R3
IS
IS+
R2
60 mV Trip
R4
C1
R1
L1
L
V
OUT
Switching
Node
Boost Component Selection for Upper FET Gate Drive
The boost (BST) pin provides for application of a higher
voltage to drive the upper FET. This voltage may be provided
by a fixed higher voltage or it may be generated with a boost
capacitor and charging diode, as shown in Figure 10. The
voltage in the boost configuration would be the summation of
the voltage from the charging diode and the output voltage
swing. Care must be taken to keep the peak voltage with
respect to ground less than 20 V peak. The capacitor should be
large enough to drive the capacitance of the top FET.
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