參數(shù)資料
型號(hào): NCP5210MNR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: 3-in-1 PWM Dual Buck and Linear DDR Power Controller
中文描述: DUAL SWITCHING CONTROLLER, 550 kHz SWITCHING FREQ-MAX, PDSO20
封裝: 6 X 5 MM, LEAD FREE, PLASTIC, QFN-20
文件頁數(shù): 12/18頁
文件大小: 183K
代理商: NCP5210MNR2G
NCP5210
http://onsemi.com
12
Switching
Frequency
Doubles
5VSTBY
or
5VDUAL
12 V
5 V
BUF_CUT
SS pin
DDQS0
MCH
State
1
2
3
4
5
6
7
8
9
10
12 13
14
15 16
17
S0
S3
S0
S5
11
2. 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has to be up first to ensure gates are in known state.
3. 12 V and 5 V supplies can ramp in either order.
4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * C
SS
/ 4 (sec).
5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground.
5. MCH ramps with the tracking of SS pin ramp, timing is 0.8 * C
SS
/ 8 (sec). VTT rises.
6. MCH SS is completed, then SS pin is released from MCH. SS pin is shorted to ground. S0 Mode.
7. S3 MODE BUF_CUT = H.
8. VTT and MCH will be turned off.
9. 12 V and 5 V ramps to 0 V.
10.Standard S3 Mode.
11.12 V and 5 V ramp back to regulation.
12.BUF_CUT goes LOW.
13.12 V UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 0.8 * C
SS
/ 8 (sec). VTT rises.
14.S0 Mode.
15.Prepare S5 Mode BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H.
16.DDQ, VTT, and MCH Turned OFF.
17.S5 Mode.
VTT
Figure 16. NCP5210 Timing Diagram
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