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參數(shù)資料
| 型號： | NCP4331DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Buck Controller for High Efficiency Post Regulation |
| 中文描述： | SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 195K |
| 代理商： | NCP4331DR2G |
NCP4331
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS
(V
CC
= 20 V, V
BST
= 7 V, HB Grounded, T
J
= 0
°
C to +125
°
C, unless otherwise specified)
Symbol
Unit
Max
Typ
Min
Rating
ERROR AMPLIFIER
V
ref
Referenced Voltage Regulation @ Pin 7 Being Open
0
°
C < T
J
< 85
°
C
-40
°
C < T
J
< 125
°
C (Guaranteed by Test from 0
°
C < T
J
< 125
°
C and
Extended to -40
°
C by Design)
0.738
0.735
0.750
0.750
0.762
0.765
V
IB
FB
Feedback Input Bias Current @ V
pin6
= V
ref
-500
-250
0
nA
BW
Gain Bandwidth
-
4
-
MHz
G
EA
Open Loop Voltage Gain
-
70
-
dB
EA
out
-EA
max
-EA
min
Pin 5 (Compensation) Voltage
V
pin6
= 0 V
V
pin6
= 1 V
3.50
-
3.70
0.05
-
0.50
V
I
source-EA
Output Source Current @ V
pin6
= 0 V
40
65
90
A
SOFT-START AND MAXIMUM DUTY-CYCLE LIMITATION (D
max
)
I
SS
Source Current @ V
SS
= 0 V to 3.5 V
40
50
63
A
V
SS
Clamp Voltage
3.5
3.7
-
V
EA
MIN
Error Amplifier Output @ V
pin5
= 0.5 V
-
0.05
0.5
V
EA
SS
Error Amplifier Output @ V
pin6
= 0 V and V
pin7
= 2 V
1.9
2.0
2.1
V
RAMP CONTROL
I
ramp
C
ramp
Current Source @ V
ramp
= 0 V to 3.5 V
40
50
63
A
V
rampH
C
ramp
Ramp Clamp
3.5
3.7
-
V
V
rampL
Low Voltage of the Ramp Saw-Tooth
-
-
100
mV
V
rampON
Ramp Voltage Enabling the High-Side Driver:
@V
pin5
= 0.5 V
@ V
pin5
= 3.5 V (Min Highest EA Value)
@ V
pin5
= 2 V
2.30
-
0.80
2.50
-
1.00
2.65
0
1.20
V
Q
RESET
Current Charge Extracted During the RESET Pulse (Note 4)
5
-
-
nC
T
RESET
Delay from SYNC Pin low to Reset Completion (a Falling Pulse Being
Applied to Pin 16)
-
200
350
ns
R
RESET
Sink Resistance of Pin 8 during the Reset Time @ I
pin8
= 10 mA (This is
the Resistance of the Switch that Discharges the C
ramp
Capacitor during
the Reset Pulse - Capability of 5 nC Min)
-
15
25
SYNCHRONIZATION BLOCK
V
SYNC
H
Synchronization Comparator Threshold (V
pin9
Rising)
2.4
2.5
2.6
V
H
SYNC
Synchronization Comparator Hysteresis
1.2
1.5
1.8
V
V
CL-SYNC
Negative Clamp Voltage of the Synchronization Pin @ I
pin16
= 2 mA
-0.3
-
0
V
T
SYNC
HS
Delay From SYNC Pin High to HS_DRV High
(A Rising PUlse Being Applied to Pin 16)
-
100
250
ns
UNDERVOLTAGE DETECTION (UVP)/SHUTDOWN
V
UVP
L
Comparator Threshold (V
pin4
Being Falling)
1.92
2.00
2.08
V
V
UVP
H
Comparator Threshold (V
pin4
Being Rising) (Note 5)
-
-
2.20
V
H
UVP
Hysteresis of the UVP Comparator
-
40
-
mV
I
UVP
UVP Current Source
15
25
30
A
IB
UVP
Bias Current
-
-
0.1
A
3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive
to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design.
4. Guaranteed by design. Tested through the R
RESET
parameter.
5. Guaranteed by characterization and design.
6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically
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