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參數(shù)資料
| 型號： | NCP4331 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Synchronous Buck Controller for High Efficiency Post Regulation |
| 中文描述： | 同步降壓控制器的高效率后調(diào)整 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 195K |
| 代理商： | NCP4331 |
NCP4331
http://onsemi.com
5
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
BST, HB
Bootstrap and “Half-Bridge” Node Inputs (Referenced to GND)
-2, +40
V
BST
HB
Bootstrap Pin Voltage Referenced to the HB Node
-0.3, +10
V
V
CC
Internal Regulator Input
-0.3, +30
V
V
in
Pins 1, 2, 3, 4, 5, 6, 7, 8 and 9
-0.3, +5
V
V
DD
Supply Voltage
-0.3, +10
V
R
JA
Thermal Resistance (TSSOP-16 and SOIC-16)
145
°
C/W
ESD Capability, Human Body Model (HBM)
2
kV
ESD Capability, Machine Model (MM) (Note 2)
200
V
T
A
Operating Temperature Range (Note 1)
-40, +125
°
C
T
Jmax
Maximum Junction Temperature
150
°
C
T
Smax
Storage Temperature Range
-65 to 150
°
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum junction temperature should not be exceeded.
2. The Machine Model ESD capability is 150 V for Pin 9.
ELECTRICAL CHARACTERISTICS
(V
CC
= 20 V, V
BST
= 7 V, HB Grounded, T
J
= 0
°
C to +125
°
C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
HIGH-SIDE OUTPUT STAGE
R
HS_source
Source Resistance @ I
source
= 100 mA
-
3
6
R
HS_sink
Sink Resistance @ I
sink
= 100 mA
-
2
4
t
r-HS
t
f-HS
Rise and Fall Times:
High-Side Output Voltage Rise Time (C
L
= 1 nF) (Note 3)
High-Side Output Voltage Fall Time (C
L
= 1 nF) (Note 3)
-
-
13
8
20
15
ns
T
LS-HS
Delay from Low-Side Gate Drive Low (High) to High-Side Drive High
(Low) (Note 6)
35
55
75
ns
LOW-SIDE OUTPUT STAGE
R
LS_source
Source Resistance @ I
source
= 100 mA
-
3
6
R
LS_sink
Sink Resistance @ I
sink
= 100 mA
-
2
4
t
r-LS
t
f-LS
Rise and Fall Times:
High-Side Output Voltage Rise Time (C
L
= 1 nF) (Note 3)
High-Side Output Voltage Fall Time (C
L
= 1 nF) (Note 3)
-
-
13
8
20
15
ns
CURRENT CONTROL ERROR AMPLIFIER (Auxiliary Error Amplifier)
IB
pin3
Noninverting Input Bias Current @ V
pin3
= V
pin2
= V
ref
-500
-100
0
nA
IB
pin2
Inverting Input Bias Current @ V
pin3
= V
pin2
= V
ref
-500
-100
0
nA
V
io
Input Offset Voltage (Note 5)
-5
1
5
mV
BW
Gain Bandwidth
-
4
-
MHz
G
EA
Open Loop Voltage Gain
-
70
-
dB
V
LL
Pin 1 Voltage if V
pin2
= 1 V and V
pin3
= 0 V, 100 A Being Sourced Into
Pin 1
0
-
0.5
V
3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive
to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design.
4. Guaranteed by design. Tested through the R
RESET
parameter.
5. Guaranteed by characterization and design.
6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically
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