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參數資料
| 型號： | NCP400FCT2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | 150 mA CMOS Low Iq Low-Dropout Voltage Regulator with Voltage Detector Output |
| 中文描述： | 1.8 V FIXED POSITIVE LDO REGULATOR, 0.2 V DROPOUT, PBGA6 |
| 封裝： | LEAD FREE, FCP-6 |
| 文件頁數： | 9/14頁 |
| 文件大小： | 106K |
| 代理商： | NCP400FCT2G |
NCP400
http://onsemi.com
9
OPERATION DESCRIPTION
Low Dropout Voltage Regulator
The low dropout voltage regulator contains a voltage
reference unit, an error amplifier, a PMOS power transistor,
resistors for setting output voltage, current limit and thermal
shutdown protection circuits.
Enable Operation
The enable pin will turn on or off the regulator. The limits
of threshold are covered in the electrical specification
section of this data sheet. If the enable is not used then the
pin should be connected to V
in
.
Voltage Detector
The NCP400 consist of a precision voltage detector that
drives a time delay generator. Figures 23 and 24 show a
timing diagram and a typical application. Initially consider
that input voltage V
in
is at a nominal level and it is greater
than the voltage detector upper threshold (V
DET+
). The
voltage at CD Pin (Pin 4) will be at the same level as Vin, and
the reset output (Pin 3) will be in the high state. If there is a
power interruption and Vin becomes significantly deficient,
it will fall below the lower detector threshold (V
DET
) and
the external time delay capacitor CD will be immediately
discharged by an internal NChannel MOSFET that
connects to Pin 4. This sequence of events causes the Reset
output to be in the low state. After completion of the power
interruption, V
in
will again return to its nominal level and
become greater than the V
DET+
. The voltage detector will
turn off the NChannel MOSFET and allow internal current
source to charge the external capacitor CD, thus creating a
programmable delay for releasing the reset signal. When the
voltage at CD Pin 4 exceeds the inverter threshold, typically
0.97 V, the reset output will revert back to its original state.
The detail reset output time delay calculation is shown in
Figure 24.
Figure 23. Timing diagram
V
in
V
DET+
V
DET
V
in
V
DET
V
in
0.97 V
0 V
Capacitor, Pin 4
Reset Output, Pin 3
Input Voltage, Pin 1
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