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參數(shù)資料
| 型號： | NCP1927DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 531K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
NCP1927
http://onsemi.com
15
sense signal to an internal ramp generated by the SoftSkip
timer instead of the feedback voltage. Since the LEB of the
FCS Pin prevents operation at nearly 0% duty ratio, the
controller instead compares the softskip ramp to an internal
sawtooth signal generated by the oscillator (not subjected to
LEB). This causes the controller to operate briefly in voltage
mode instead of current mode. Once the CS signal reaches
the feedback voltage, the controller resumes normal
operation in current mode. The skip mode block diagram is
shown in Figure 14. The ramp timing and overall timing
diagrams are shown in Figures 15 and 16.
Figure 14. Skip Cycle with SoftSkip Architecture
FDRV stage
FCS
S
R
Q
Softskip ramp
FFB
Reset
Oscillator
Sawtooth
t
LEB
K
FFB
V
FSKIP
D
MAX
V
FSKIP
t
SSKIP
+
+
Figure 15. Skip Cycle with SoftSkip Timing Diagram
Time
V
FFB
V
FSKIP(HYS)
Time
FDRV
Time
CS Setpoint
SoftSkip
Enters
SoftSkip
SoftSkip
Exits
SoftSkip
V
FSKIP
V
fold
During the SoftSkip duration if the feedback voltage
goes above V
fold
, the SoftSkip ends instantaneously
allowing the controller to operate in current mode.
This transient load detection feature avoids large output
drops if a load transient occurs while the controller is in skip
mode.
Figure 16. SoftSkip Timing Diagram
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