參數(shù)資料
型號: NCP1351ADR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Variable Off Time PWM Controller
中文描述: 0.4 A SWITCHING CONTROLLER, PDSO8
封裝: LEAD FREE, SOIC-8
文件頁數(shù): 14/19頁
文件大?。?/td> 222K
代理商: NCP1351ADR2G
NCP1351
http://onsemi.com
14
Figure 17. The Internal Fault Management Differs Depending on the Considered Version
+
+
C1
100n
V
CC
I
FB
C
timer
100nF
V
CC
R1
2.5k
+
+
+
V
timer
5
I
timer
10
20 s
Filter
P
on
Reset
I
FB
D
FB
I
FB
Timer
L
aux
CV
CC
I
CC
V
CC
D
aux
I
FB
< 40 A = Low
Else = High
DRV Pulses
V
CC
==
VCC
(min)
Reset
Q
Q
S
to DRV
Stage
AutoRecovery B Version
+
+
C1
100n
V
CC
I
FB
C
timer
100nF
V
CC
R1
2.5k
+
+
+
V
timer
5
I
timer
10
20 s
Filter
P
on
Reset
I
FB
D
FB
I
FB
Timer
L
aux
CV
CC
I
CC
V
CC
D
aux
I
FB
< 40 A = Low
Else = High
SCR Delatches When
I
SCR
< ICC
latch
(Few A)
Latched A Version
6V
FB
FB
R
Knowing both the ending voltage and the charge current,
we can easily calculate the timer capacitor value for a given
delay. Suppose we need 40 ms. In that case, the capacitor is
simply:
11.7
Ctimer
ItimerT
Vtimer
40 m
5
94 nF
(eq. 15)
Select a 100 nF value.
Latch Input
The NCP1351 features a patented circuitry which
prevents the FB input to be of low impedance before the Vcc
reaches the VCC
ON
level. As such, the circuit can work in
a primary regulation scheme. Capitalizing on this typical
option, Figure 18 shows how to insert a zener diode in series
with the optocoupler emitter pin. In that way, the current
biases the zener diode and offers a nice reference voltage,
appearing at the loop closure (e.g. when the output reaches
the target). Yes, you can use this reference voltage to supply
a NTC and form a cheap OTP protection.
Figure 18. The Latch Input Offers Everything Needed
to Implement an OTP Circuit. Another Zener Can
Help combining an OVP Circuit if Necessary
C2
100n
V
CC
R1
2.5k
C1
100nF
Latch
FB
C3
100nF
5V
OVP
D2
R
pulldown
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