參數(shù)資料
型號(hào): NCP1083DEG
廠商: ON Semiconductor
文件頁(yè)數(shù): 13/18頁(yè)
文件大小: 257K
描述: IC CONV CTLR POE-PD 40W 20-TSSOP
標(biāo)準(zhǔn)包裝: 74
類(lèi)型: 以太網(wǎng)供電開(kāi)關(guān)(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪(fǎng)問(wèn))
內(nèi)部開(kāi)關(guān):
電流限制: 1.1A
電源電壓: 0 V ~ 57 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 20-TSSOP-EP
包裝: 管件
NCP1083
http://onsemi.com
13
" The PSE skipped the classification phase.
" The PSE performed a one event hardware classification
(it can be a IEEE 802.3af or a 802.3at compliant PSE
with Layer 2 engine).
" The PSE performed a two event hardware classification
but it did not properly control the input voltage in the
mark voltage window, (for example it crossed the reset
range).
Power Mode
When the classification handshake is completed, the
PSE and PD devices move into the operating mode.
Under Voltage Lock Out (UVLO)
The NCP1083 incorporates an under voltage lock out
(UVLO) circuit which monitors the input voltage and
determines when to apply power to the DCDC controller.
To use the default settings for UVLO (see Table 3), the pin
UVLO must be connected to VPORTN
1,2
. In this case the
signature resistor has to be placed directly between
VPORTP and VPORTN
1,2
, as shown in Figure 11.
Figure 11. Default UVLO Settings
UVLO
VPORTP
VPORTN1,2
NCP1083
VPORT
Rdet
To define the UVLO threshold externally, the UVLO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN
1,2
 as shown in
Figure 12. The series resistance value of the external
resistors must add to 25.5 kW and replaces the internal
signature resistor.
Figure 12. External UVLO Configuration
UVLO
VPORTN1,2
NCP1083
VPORT
R2
R1
VPORTP
For a Vuvlo_on desired turnon voltage threshold, R1 and
R2 can be calculated using the following equations:
R1 ) R2 + R
det
R2 +
1.2
V
ulvo_on
  R
det
When using the external resistor divider, the NCP1083 has
an external reference voltage hysteresis of 15 percent typical.
Auxiliary Supply Support
To support applications connected to nonPoE enabled
networks and minimize the bill of materials, the NCP1083
supports drawing power from an external supply. The
NCP1083 supports the IEEE 802.3af/at standard when PoE
power sourcing is available and acts as a regular DCDC
converter when there is no power source available on the
Ethernet cable as shown in Figure 13.
Auxiliary supply support can be implemented in three
ways depending on where the auxiliary supply is injected.
The front, rear and direct auxiliary supply configurations are
explained in more detail in the application note AND9080.
UVLO
VPORTN1,2
NCP1083
VPORTP
Rdet1
Raux2
VAUX(+)
Rdet2
Pass
Switch
RTN
Raux1
Raux3
AUX
D1
D2
POE(+)
POE()
VPORT
Cpd
DCDC Stage
VAUX()
to VPORTN1,2 (Front AUX Configuration)
to RTN (Rear AUX Configuration)
Or
Figure 13. Front and Rear Auxiliary Supply Input with Support for Very Low Input Voltages
Optional 
for very low
VAUX only
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