![](http://datasheet.mmic.net.cn/230000/NCP1012ST65T3_datasheet_15596067/NCP1012ST65T3_17.png)
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
http://onsemi.com
17
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
Figure 26. The DrainSource Wave Shall Always be Positive . . .
1.004M
1.011M
1.018M
1.025M
1.032M
50.0
50.0
150
250
350
> 0 !!
1. In any case, the lateral MOSFET bodydiode shall
never be forward biased, either during startup
(because of a large leakage inductance) or in
normal operation as shown by Figure 26.
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N · (Vout
Vf)
Vinmin
operating from a 120 V DC rail, with a delivery of 12 V, we
can select a reflected voltage of 100 Vdc maximum:
120–100 > 0. Therefore, the turn ratio Np:Ns must be
smaller than 100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see
later on how it affects the calculation.
2. A currentmode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a dutycycle greater
than 50%. As a result, we recommend to operate
the device in DCM only, whatever dutycycle it
implies (max = 65%). However, CCM operation
with dutycycles below 40% is possible.
3. Lateral MOSFETs have a poorly dopped
bodydiode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications,
a simple capacitor can also be used since
(eq. 14)
. For instance, if
Vdrain max
Vin
N · (Vout
Vf)
Ip ·
Lf
Ctot
(eq. 15)
, where Lf is the leakage inductance,
Ctot is the total capacitance at the drain node
(which is increased by the capacitor wired between
drain and source), N the Np:Ns turn ratio, Vout the
output voltage, Vf the secondary diode forward
drop and finally, Ip the maximum peak current.
Worse case occurs when the SMPS is very close to
regulation, e.g. the Vout target is almost reached
and Ip is still pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line.
When the switch closes, Vin is applied across the primary
inductance Lp until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
Lp · Ip
ton
Vin
(eq. 16)
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across
Lp, resetting the transformer core with a slope of
N · (Vout
Vf)
Lp
Lp · Ip
N · (Vout
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a deadtime after the
core is reset, but rather immediately restart. The switching
time can be expressed by:
. toff, the OFF time is thus:
toff
Vf)
(eq. 17)
Tsw
toff
ton
Lp · Ip ·
1
Vin
1
N · (Vout
Vf)
(eq. 18)