參數資料
型號: NCN6004AFTBR2
廠商: ON Semiconductor
文件頁數: 34/40頁
文件大小: 0K
描述: IC INTERFACE SAM/SIM DUAL 48TQFP
標準包裝: 1
應用: PC,PDA
接口: 微控制器
電源電壓: 1.8 V ~ 5.5 V
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-TQFP(7x7)
包裝: 剪切帶 (CT)
安裝類型: 表面貼裝
其它名稱: NCN6004AFTBR2OSCT
NCN6004A
http://onsemi.com
4
PIN DESCRIPTION
Pin
Symbol
Type
Description
1
A0
INPUT
This pin is combined with CS, A1, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
2
A1
INPUT
This pin is combined with CS, A0, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
3
A2
INPUT
This pin is combined with CS, A0, A1, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
4
A3
INPUT
This pin is combined with CS, A0, A1, A2, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by the
internal STATUS register (Table 1).
5
CARD_SEL
INPUT
This pin provides logic identification of the Card #A/Card #B external smart card. The
logic signal is set up by the external microcontroller.
CARD_SEL = High
→ selection of the Smart Card A connected to pins 20, 21, 22, 23, 24,
29 and 30 (respectively CRD_DET_A, CRD_C8_A, CRD_C4_A, CRD_RST_A,
CRD_IO_A, CRD_VCC_A and CRD_CLK_A).
CARD_SEL = Low
→ selection of the Smart Card B connected to pins 41, 39, 40, 31, 38,
37, and 32 (respectively CRD_DET_B, CRD_C4_B, CRD_C8_B, CRD_CLK_B,
CRD_RST_B, CRD_IO_B, and CRD_VCC_B).
6
PGM
DIGITAL INPUT
This pin is combined with CS, A0, A1, A2, A3, and CARD_SEL to program the chip mode
of operation and to read the data provided by the internal STATUS register (Figure 4 and
Table 1).
PGM = H
→ the NCN6004A is under normal operation and all the data with the external
card can be exchanged using any of the Smart Card A or Smart Card B Lines
PGM = Low
→ the NCN6004A runs the programming mode and related parameters can
be re programmed according to a given need. In this case, the related card side logic
signals are latched in their previous states and no transaction can occurs.
The programmed states are latched upon the PGM rising slope (Figure 4).
7
CS
DIGITAL INPUT
This pin provides the Chip Select Function for the NCN6004A device.
CS = High
→ Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B,
C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are disabled, the pre activated CRD_VCC
maintains it’s currently programmed value.
CS = Low
→ Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RESET_B,
C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are activated, all the functions being
available.An internal pull up resistor, connected to VCC, provides a logic bias when the
external
mP is in the high impedance state.
8
PWR_ON
DIGITAL INPUT
This pin activates or deactivates the DC/DC converter selected by CARD_SEL upon
positive/negative going transient.
PWR_ON = Positive going High
→ DC/DC Activated
PWR_ON = Negative going L
→ DC/DC switched Off, no power is applied to the
associated output CRD_VCC pin.
Since uncontrolled action could take place during the rise voltage of the related
CRD_VCC_x output, care must be observed to avoid a PWR_ON negative going
transient during this period of time. To avoid any logical latch up, using a minimum 1.0 ms
delay is recommended prior to power down the related DC/DC converter following a
power up command (Figure 12).
9
I/O_A
INPUT/OUTPUT
This pin carries the data transmission between an external microcontroller and the
external smart card #A.
A builtin bidirectional level translator adapts the signal flowing between the card and
the MCU. The level translator is enabled when CS = Low. Since a dedicated line is used
to communicate the data between the MPU and the smart card, the user can activate the
two channels simultaneously, assuming the
mP provides a pair of I/O lines.
When MUX_MODE = High, this pin provides an access to either card A or B I/O by
means of CARD_SEL selection bit. On the other hand, the internal pull up resistor is
automatically disconnected when MUX_MODE = High, avoiding a current overload on
the I/O line, regardless of the EN_RPU logic level.
This pull up resistor is under the EN_RPU control when MUX_MODE = Low.
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