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參數(shù)資料
| 型號(hào)： | NC7WP02L8X |
| 廠(chǎng)商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE NOR ULP DUAL 2IN 8MCRPAK |
| 產(chǎn)品變化通告： | Die Material, Mold Compound Change 03/Oct/2008 |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | 7WP |
| 邏輯類(lèi)型： | 或非門(mén) |
| 電路數(shù)： | 2 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 0.9 V ~ 3.6 V |
| 電流 - 靜態(tài)（最大值）： | 0.9µA |
| 輸出電流高，低： | 2.6mA，2.6mA |
| 邏輯電平 - 低： | 0.7 V ~ 0.9 V |
| 邏輯電平 - 高： | 1.6 V ~ 2.1 V |
| 額定電壓和最大 CL 時(shí)的最大傳播延遲： | 7ns @ 3V ~ 3.6V，30pF |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 8-MicroPak? |
| 封裝/外殼： | 8-XFQFN |
| 包裝： | 帶卷 (TR) |
2005 Fairchild Semiconductor Corporation
DS500811
www.fairchildsemi.com
October 2003
Revised January 2005
NC7WP02
T
inyLogi
c
ULP
Dual
2-I
nput
NOR
Gate
NC7WP02
TinyLogic
ULP Dual 2-Input NOR Gate
General Description
The
NC7WP02
is
a dual 2-Input NOR Gate from
Fairchild’s Ultra Low Power (ULP) series of TinyLogic
.
Ideal for applications where battery life is critical, this prod-
uct is designed for ultra low power consumption within the
VCC operating range of 0.9V to 3.6V VCC.
The internal circuit is composed of a minimum of inverter
stages, including the output buffer, to enable ultra low static
and dynamic power.
The NC7WP02 is designed for optimized power and
speed, and is fabricated with an advanced CMOS technol-
ogy to achieve high speed operation while maintaining
extremely low CMOS power dissipation.
Features
s Space saving US8 package
s Ultra small MicroPak
Pb-Free package
s 0.9V to 3.6V VCC supply operation
s 3.6V overvoltage tolerant I/O’s at VCC from 0.9V to 3.6V
s tPD
3 ns typ for 3.0V to 3.6V VCC
4 ns typ for 2.3V to 2.7V VCC
5 ns typ for 1.65V to 1.95V VCC
6 ns typ for 1.40V to 1.60V VCC
9 ns typ for 1.10V to 1.30V VCC
24 ns typ for 0.90V VCC
s Power-Off high impedance inputs and outputs
s Static Drive (IOH/IOL)
±2.6 mA @ 3.00V V
CC
±2.1 mA @ 2.30V V
CC
±1.5 mA @ 1.65V V
CC
±1.0 mA @ 1.40V V
CC
±0.5 mA @ 1.10V V
CC
±20 A@ 0.9V V
CC
s Low noise switching using design techniques of
Quiet Series
noise/EMI reduction circuitry
s Ultra low dynamic power
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Battery Life vs. VCC Supply Voltage
TinyLogic ULP and ULP-A with up to 50% less power consumption can
extend your battery life significantly.
Battery Life
= (V
battery *Ibattery*.9)/(Pdevice)/24hrs/day
Where, Pdevice = (ICC * VCC) + (CPD + CL) * VCC
2 * f
Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and
derated 90% and device frequency at 10MHz, with CL = 15 pF load
TinyLogic
is a registered trademark, and Quiet Series and MicroPak are trademarks of Fairchild Semiconductor Corporation.
Order Number
Product
Package Description
Supplied As
Package
Code
Number
Top Mark
NC7WP02K8X
MAB08A
WP02
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WP02L8X
MAC08A
Y4
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NC7WP04 | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:TinyLogic ULP Dual Inverter |
| NC7WP04L6X | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:TinyLogic ULP Dual Inverter |
| NC7WP04P6X | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:TinyLogic ULP Dual Inverter |
| NC7WP07 | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:TinyLogic-R ULP Dual Buffer (Open Drain Output) (Preliminary) |
| NC7WP07L6X | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:TinyLogic-R ULP Dual Buffer (Open Drain Output) (Preliminary) |
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