參數(shù)資料
型號(hào): NC7SV00FHX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 門電路
中文描述: AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6
封裝: 1 X 1 MM, 0.35 MM PITCH, GREEN, MO-252, MICROPAK2-6
文件頁數(shù): 10/11頁
文件大?。?/td> 572K
代理商: NC7SV00FHX
2002 Fairchild Semiconductor Corporation
NC7SV00 Rev. 1.0.3
www.fairchildsemi.com
10
N
Physical Dimensions
1.00
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
0.05 C
A
B
0.55MAX
0.05 C
C
0.35
0.09
0.19
1
2
3
0.35
0.25
5X
6X
DETAIL A
0.60
(0.08)
4X
(0.05) 6X
0.40
0.30
0.075X45°
CHAMFER
5X 0.40
0.35
1X 0.45
6X 0.19
TOP VIEW
BOTTOM VIEW
0.66
0.10
.05 C
C B A
0.89
PIN 1
MIN 250uM
0.05 C
2X
2X
1.00
E. DRAWING FILENAME AND REVISION: MGF06AREV3
0.52
0.73
0.57
0.20 6X
1X
5X
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
0.90
DETAIL A
PIN 1 LEAD SCALE: 2X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
6
5
4
0.35
(0.08) 4X
SIDE VIEW
Figure 9.
6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Cavity Number
Cavity Status Cover Type Status
FHX
Leader (Start End)
Carrier
Trailer (Hub End)
125 (Typical)
5000
75 (Typical)
Empty
Filled
Empty
Sealed
Sealed
Sealed
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