Table 6. DC CHARACTERISTICS (VDD =" />
參數資料
型號: NBXDBA012LN1TAG
廠商: ON Semiconductor
文件頁數: 3/6頁
文件大小: 0K
描述: IC CLK XO 106.25/212.5MHZ 6CLCC
產品培訓模塊: XO Replacement Overview
標準包裝: 1
系列: PureEdge™
類型: 振蕩器 - 晶體
頻率: 106.25MHz,212.5MHz
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 82mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 6-CLCC
包裝: 標準包裝
供應商設備封裝: 6-CLCC(7x5)
安裝類型: 表面貼裝
其它名稱: NBXDBA012LN1TAGOSDKR
NBXDBA012
http://onsemi.com
3
Table 6. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = 40°C to +85°C)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
IDD
Power Supply Current (Note 2)
82
100
mA
VIH
OE and FSEL Input HIGH Voltage
2000
VDD
mV
VIL
OE and FSEL Input LOW Voltage
GND 300
800
mV
IIH
Input HIGH Current
OE
FSEL
100
+100
mA
IIL
Input LOW Current
OE
FSEL
100
+100
mA
VOH
Output HIGH Voltage (Note 2)
VDD = 3.3 V
VDD1145
2155
VDD895
2405
mV
VOL
Output LOW Voltage (Note 2)
VDD = 3.3 V
VDD1945
1355
VDD1600
1700
mV
VOUTPP
Output Voltage Amplitude (Note 2)
700
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to VDD2 V.
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = 40°C to +85°C)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
fCLKOUT
Output Clock Frequency
FSEL = HIGH
106.25
MHz
FSEL = LOW
212.5
Df
Frequency Stability NBXDBA012
(Note 4)
±50
ppm
FNOISE
PhaseNoise Performance
100 Hz of Carrier
108/101
dBc/Hz
fCLKout = 106.25 MHz/212.5 MHz
1 kHz of Carrier
126/120
dBc/Hz
(See Figures 3 and 4)
10 kHz of Carrier
133/126
dBc/Hz
100 kHz of Carrier
133/127
dBc/Hz
1 MHz of Carrier
140/133
dBc/Hz
10 MHz of Carrier
162/160
dBc/Hz
tjit(F)
RMS Phase Jitter
12 kHz to 20 MHz
0.4
0.9
ps
tjitter
Cycle to Cycle, RMS
1000 Cycles
2
8
ps
Cycle to Cycle, PeaktoPeak
1000 Cycles
12
30
ps
Period, RMS
10,000 Cycles
1
4
ps
Period, PeaktoPeak
10,000 Cycles
8
20
ps
tOE/OD
Output Enable/Disable Time
200
ns
tDUTY_CYCLE
Output Clock Duty Cycle
(Measured at Cross Point)
48
50
52
%
tR
Output Rise Time (20% and 80%)
(See Figures 5 and 6)
250
400
ps
tF
Output Fall Time (80% and 20%)
(See Figures 5 and 6)
250
400
ps
tstart
Startup Time
1
5
ms
Aging
1st Year
3
ppm
Every Year After 1st
1
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to VDD2 V. See Figure 7.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
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