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參數(shù)資料
| 型號(hào)： | NBSG86ABAHTBG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA DIFF DIV/2 16FCBGA |
| 產(chǎn)品變化通告： | Product Obsolescence 05/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 邏輯類型： | 可配置多功能 |
| 電路數(shù)： | 2 |
| 輸入數(shù)： | 2 |
| 施密特觸發(fā)器輸入： | 無 |
| 輸出類型： | 差分 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-LBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 16-FCBGA（4x4） |
| 包裝： | 帶卷 (TR) |
NBSG86A
http://onsemi.com
2
VTD1 D1
D1 VTD1
VTD0 D0
D0 VTD0
VEE
Q
VCC
OLS
SEL
VTSEL
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG86A
Exposed Pad
(EP)
Figure 1. QFN16 Pinout (Top View)
Table 1. Pin Description
Pin
Name
I/O
Description
QFN
1
OLS
(Note 3)
Input
Input Pin for the Output Level Select (OLS). See Table 2.
2
SEL
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Select Logic Input.
3
SEL
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Select Logic Input.
4
VTSEL
5
VTD1
6
D1
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input 1. Internal 75 kW to VEE.
7
D1
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input 1. Internal 75 kW to VEE and 36.5 kW to VCC.
8
VTD1
9
VCC
Positive Supply Voltage (Note 2)
10
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC
2 V.
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC 2 V
12
VEE
Negative Supply Voltage (Note 2)
13
VTD0
14
D0
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input 0. Internal 75 kW to VEE and 36.5 kW to VCC.
15
D0
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input 0. Internal 75 kW to VEE.
16
VTD0
EP
The Exposed Pad (EP) and the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is electrically connected to the die but may be electrically and
thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
or left open, and if no signal is applied then the device will be susceptible to selfoscillation.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and VCC VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE.
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