VCC Q FlipFlop (DIV/2) Flip" />
參數(shù)資料
型號(hào): NBSG53AMNR2G
廠商: ON Semiconductor
文件頁數(shù): 12/18頁
文件大小: 0K
描述: IC FLIP FLOP DIFF CLOCK 16QFN
產(chǎn)品變化通告: Revision of Device Specifications 02/Oct/2008
標(biāo)準(zhǔn)包裝: 3,000
功能: 復(fù)位
類型: D 型總線
輸出類型: 差分
元件數(shù): 1
每個(gè)元件的位元數(shù): 2
頻率 - 時(shí)鐘: 8GHz
觸發(fā)器類型: 正,負(fù)
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: NBSG53AMNR2GOS
NBSG53A
http://onsemi.com
3
Figure 3. Simplified Logic Diagram
D
SEL
CLK
VTD
VCC
Q
FlipFlop
(DIV/2)
FlipFlop
(DFF)
R
D
VTD
OLS
R
Q
VEE
VTCLK
R
75 kW
50 W
0
1
2
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS
Q/Q VPP
OLS Sensitivity
VCC
800 mV
OLS 75 mV
VCC 0.4 V
200 mV
OLS $ 150 mV
VCC 0.8 V
600 mV
OLS $ 100 mV
VCC 1.2 V
0
OLS $ 75 mV
VEE (Note 4)
400 mV
OLS + 100 mV
Float
600 mV
N/A
4. When an output level of 400 mV is desired and
VCC VEE > 3.0 V, 2.0 kW resistor should be connected from
OLS to VEE.
Table 3. TRUTH TABLE
R
SEL
D
CLK
Q
Function
H
x
L
Reset
L
H
L
Z
L
DFF
L
H
Z
H
DFF
L
x
Z
Q
DIV/2
Z = LOW to HIGH Transition
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK, VTD and VTCLK, VTD to VCC
LVDS
Connect VTCLK, VTD and VTCLK, VTD Together
ACCOUPLED
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal
VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification.
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