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參數(shù)資料
| 型號： | NBSG53AMNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS |
| 中文描述： | 53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, QFN-16 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 133K |
| 代理商： | NBSG53AMNR2 |
NBSG53A
http://onsemi.com
10
Table 11. AC CHARACTERISTICS for QFN16
V
CC
= 0 V; V
EE
= 3.465 V to 2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
(See Figures 5, 7, 9, 10, and 11)
(Note 30)
DFF
DIV/2
8
10
8
10
8
10
GHz
t
PLH
,
t
PHL
Propagation Delay to Output Differential
(Note 34)
CLK
→
Q, Q
SEL
→
Q, Q
R
→
Q, Q D
IN
/2
DFF
150
160
215
195
215
190
280
270
285
280
375
345
150
160
215
195
215
190
280
270
285
280
375
345
150
160
215
195
215
190
280
270
285
280
375
345
ps
t
SKEW
Duty Cycle Skew (Notes 31 and 33) DFF
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
f
in
8 GHz
(See Figures 4 and 6) (Note 30)
PeaktoPeak Data Dependent Jitter
f
in
= 8 Gb/s
0.5
TBD
1
0.5
TBD
1
0.5
TBD
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% 80%)
@ 1 GHz
Q, Q
(OLS = V
CC
)
(OLS = V
CC
0.4 V)
(OLS = V
CC
0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
ps
t
s
t
h
Setup Time
D
→
CLK
30
14
30
10
30
13
ps
Hold Time
D
→
CLK
25
12
25
7
25
0
ps
t
rr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30.Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 to
V
2.0 V. Input edge rates is 40 ps (20% 80%).
31.See Figure 14. t
= |t
t
PHL
| for a nominal 50% differential clock input waveform.
32.V
INPP
(MAX) cannot exceed V
CC
EE
(Applicable only when V
CC
V
EE
< 2600 mV).
33.See Figure 10. Duty Cycle % vs. Frequency.
34.For all OLS Configuration.
**When an output level of 400 mV is desired and V
CC
V
EE
> 3.0 V, a 2 k resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA16 have maximum ambient temperature specification of 70
°
C and devices packaged in QFN16 have
maximum ambient temperature specification of 85
°
C.
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| NBSG72AMN/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2.5V/3.3V_SiGe Differential 2 X 2 Crosspoint Switch with Output Level Select |
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