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參數(shù)資料
| 型號(hào)： | NBSG53ABAR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP-FLOP DIFF CLOCK 16FCBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Aug/2008 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 2 |
| 頻率 - 時(shí)鐘： | 8GHz |
| 觸發(fā)器類型： | 正，負(fù) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-LBGA，F(xiàn)CBGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NBSG53ABAR2OSDKR |
NBSG53A
http://onsemi.com
2
VTD
CLK
VTCLK
VCC
R
VTCLK
D
VTD
VCC
VEE
SEL
OLS
Q
A
B
C
D
12
3
4
Figure 1. BGA16 Pinout (Top View)
VTD
D
VTD
VCC
R
SEL OLS
VEE
Q
VCC
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
BGA
QFN
C2
1
VTCLK
Internal 50 W Termination Pin. See Table 4.
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
B2
4
VTCLK
Internal 50 W Termination Pin. See Table 4.
A1
5
VTD
Internal 50 W termination pin. See Table 4.
A2
6
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
A3
7
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
A4
8
VTD
Internal 50 W Termination Pin. See Table 4.
D1,B3
9,16
VCC
Positive Supply Voltage
B4
10
Q
RSECL Output
NonInverted Differential Output. Typically Terminated with 50 W Resistor
to VTT = VCC 2 V.
C4
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC 2 V.
C3
12
VEE
Negative Supply Voltage
D4
13
OLS*
Input
Input Pin for the Output Level Select (OLS). See Table 2.
D3
14
SEL
LVECL, LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 kW to VEE.
D2
15
R
LVECL, LVCMOS,
LVTTL Input
Reset D FlipFlop. Internal 75 kW to VEE.
N/A
EP
The Exposed Pad (EP) and the QFN16 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heatsinking conduit. The pad is not
electrically connected to the die but may be electrically and thermally
connected to VEE on the PC board.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heatsinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination
voltage, and if no signal is applied then the device will be susceptible to selfoscillation.
3. When an output level of 400 mV is desired and VCC VEE > 3.0 V, 2KW resistor should be connected from OLS pin to VEE.
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| NBSG53AMNG | 功能描述:觸發(fā)器 2.5V/3.3V SiGe Diff Clock/Divider RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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