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參數(shù)資料
| 型號(hào)： | NBSG53ABAR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS |
| 中文描述： | 53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16 |
| 封裝： | 4 X 4 MM, PLASTIC, FCBGA-16 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 133K |
| 代理商： | NBSG53ABAR2 |
NBSG53A
http://onsemi.com
2
VTD
CLK
CLK
VTCLK
V
CC
R
VTCLK
D
D
VTD
V
CC
V
EE
SEL
OLS
Q
Q
A
B
C
D
1
2
3
4
Figure 1. BGA16 Pinout
(Top View)
VTD
D
D
VTD
V
CC
R
SEL OLS
V
EE
Q
Q
V
CC
VTCLK
CLK
CLK
VTCLK
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 2. QFN16 Pinout
(Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
VTCLK
I/O
Description
C2
1
Internal 50 Termination Pin. See Table 4.
C1
2
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
B1
3
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
B2
4
VTCLK
Internal 50 Termination Pin. See Table 4.
A1
5
VTD
Internal 50 termination pin. See Table 4.
A2
6
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
A3
7
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
A4
8
VTD
Internal 50 Termination Pin. See Table 4.
D1,B3
9,16
V
CC
Q
Positive Supply Voltage
B4
10
RSECL Output
Inverted Differential Output. Typically Terminated with 50 Resistor to
V
TT
= V
CC
2 V.
C4
11
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50 Resistor to
V
TT
= V
CC
2 V.
C3
12
V
EE
OLS*
Negative Supply Voltage
D4
13
Input
Input Pin for the Output Level Select (OLS). See Table 2.
D3
14
SEL
LVECL,
LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 k to V
EE
.
D2
15
R
LVECL,
LVCMOS,
LVTTL Input
Reset D FlipFlop. Internal 75 k to V
EE
.
N/A
EP
Exposed Pad. (Note 1)
1. All V
and V
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heatsinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-
age, and if no signal is applied then the device will be susceptible to selfoscillation.
3. When an output level of 400 mV is desired and V
CC
V
EE
> 3.0 V, 2K resistor should be connected from OLS pin to V
EE
.
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