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參數(shù)資料
| 型號： | NBC12429A |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| 中文描述： | 3.3V/5V的可編程鎖相環(huán)路合成時鐘發(fā)生器（3.3V/5V的可編程PLL頻率合成時鐘發(fā)生器） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 351K |
| 代理商： | NBC12429A |
NBC12429, NBC12429A
http://onsemi.com
14
There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscopeandobservethevariationsinperiod--to--period
or cycle--to--cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowedtotracesufficientcycles,itispossibletodetermine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peak--to--peak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post--processing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS--series oscilloscopes have superb jitter
analysis capabilities on non--contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single--shot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
This test process can be correlated to earlier test methods
and is more accurate. All of the jitter data reported on the
NBC12429 and NBC12429A was collected in this manner.
Figure 13 shows the jitter as a function of the output
frequency.Thegraphshowsthatforoutputfrequenciesfrom
25 to 400 MHz the jitter falls within the
20 ps
peak--to--peak specification. The general trend is that as the
output frequency is increased, the output edge jitter will
decrease.
Figure 12 illustrates the RMS jitter performance of the
NBC12429 and NBC12429A across specified VCO
frequencyrange.Notethatthejitterisafunctionofboththe
output frequency as well as the VCO frequency. However,
theVCOfrequencyshowsamuchstrongerdependence.The
data presented has not been compensated for trigger jitter.
Long--Term Period Jitter
is the maximum jitter
observedattheendofaperiod’sedgewhencomparedtothe
positionoftheperfectreferenceclock’sedgeandisspecified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
variesbyapplicationbuttheJEDECspecis10,000observed
cycles.
The NBC12429 and NBC12429A exhibit long term and
cycle--to--cycle jitter, which rivals that of SAW based
oscillators. This jitter performance comes with the added
flexibility associated with a synthesizer over a fixed
frequency oscillator. The jitter data presented should
provide users with enough information to determine the
effectontheiroveralltimingbudget.Thejitterperformance
meets the needs of most system designs while adding the
flexibilityoffrequencymarginingandfieldupgrades.These
features are not available with a fixed frequency SAW
oscillator.
Figure 12. RMS Jitter vs. VCO Frequency
VCO FREQUENCY (MHz)
200
250
300
350
400
25
20
15
10
5
0
R
N = 1
N = 8
N = 2
N = 4
Figure 13. RMS Jitter vs. Output Frequency
25
20
15
10
5
0
R
400
350
300
250
200
150
100
50
OUTPUT FREQUENCY (MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NBC12430 | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| NBC12430A | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| NBC12439A | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| NBC12439 | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時鐘發(fā)生器) |
| NBSG11BA | 2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NBC12429AFA | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12429AFAG | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12429AFAR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| NBC12429AFAR2G | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12429AFN | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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