參數(shù)資料
型號: NB7V586MMNG
廠商: ON Semiconductor
文件頁數(shù): 1/8頁
文件大小: 0K
描述: IC CLK/DTA BUFF MUX TRNSLA 32QFN
標準包裝: 74
系列: GigaComm™
類型: 扇出緩沖器(分配),多路復用器,變換器,數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 6GHz
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設(shè)備封裝: 32-QFN(5x5)
包裝: 管件
Semiconductor Components Industries, LLC, 2008
September, 2008 Rev. 0
1
Publication Order Number:
NB7V586M/D
NB7V586M
1.8V Differential 2:1 Mux
Input to 1.2V/1.8V 1:6 CML
Clock/Data Fanout Buffer /
Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB7V586M is a differential 1to6 CML Clock/Data
Distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50
W
termination resistors and will accept differential LVPECL, CML, or
LVDS logic levels (see Figure 12). The INx/INx inputs and core logic
are powered with a 1.8 V supply. The NB7V586M produces six
identical differential CML output copies of Clock or Data. The outputs
are configured as three banks of two differential pair. Each bank (or all
three banks) have the flexibility of being powered by any combination
of either a 1.8 V or 1.2 V supply.
The 16 mA differential CML output structure provides matching
internal 50
W source terminations and 400 mV output swings when
externally terminated with a 50
W resistor to VCCOx (see Figure 11).
The 1:6 fanout design was optimized for low output skew and
minimal jitter and is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications operating
up to 6 GHz or 10 Gb/s typical. The VREFAC reference outputs can be
used to rebias capacitorcoupled differential or singleended input
signals.
The NB7V586M is offered in a low profile 5x5 mm 32pin PbFree
QFN package. Application notes, models, and support documentation
are available at www.onsemi.com.
The NB7V586M is a member of the GigaComm
family of high
performance clock products.
Features
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS, Max
Low Skew 1:6 CML Outputs, 20 ps Max
2:1 MultiLevel Mux Inputs
175 ps Typical Propagation Delay
50 ps Typical Rise and Fall Times
Differential CML Outputs, 330 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 1.89 V
Operating Range: VCCOx = 1.14 V to 1.89 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5 mm x 5 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
MARKING
DIAGRAM*
QFN32
MN SUFFIX
CASE 488AM
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
SIMPLIFIED LOGIC DIAGRAM
32
1
NB7V
586M
AWLYYWW
G
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = PbFree Package
Q0
Q1
Q2
Q3
Q4
Q5
VCCO1
VCCO2
VCCO3
VCC
SEL
VREFAC0
IN0
VT0
IN0
IN1
VT1
IN1
VREFAC1
VCC
GND
0
1
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