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參數(shù)資料
| 型號(hào)： | NB7L86MMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC GATE MULTI FUNCT DIFF 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 邏輯類(lèi)型： | 可配置多功能 |
| 電路數(shù)： | 2 |
| 輸入數(shù)： | 2 |
| 施密特觸發(fā)器輸入： | 無(wú) |
| 輸出類(lèi)型： | 差分 |
| 電源電壓： | 2.4 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB7L86M
http://onsemi.com
2
VTD1 D1
D1 VTD1
VTD0 D0
D0 VTD0
VEE
Q
VCC
SEL
VTSEL
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L86M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1, 9
VCC
Power Supply
Positive supply voltage. All VCC pins must be externally connected to power
supply to guarantee proper operation.
2
SEL
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Inverted differential select logic input.
3
SEL
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Noninverted differential select logic Input.
4
VTSEL
5
VTD1
6
D1
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Noninverted differential clock/data input D1. (Note 1)
7
D1
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Inverted differential clock/data input D1. (Note 1)
8
VTD1
10
Q
CML Output
Noninverted output with internal 50 W source termination resistor. (Note 2)
11
Q
CML Output
Inverted output with internal 50 W source termination resistor. (Note 2)
12
VEE
Power Supply
Negative supply voltage. All VEE pins must be externally connected to power
supply to guarantee proper operation.
13
VTD0
Internal 50 W termination pin for D0. (Note 1)
14
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Noninverted differential clock/data input D0. (Note 1)
15
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS Input
Noninverted differential clock/data input D0. (Note 1)
16
VTD0
Internal 50 W termination pin for D0. (Note 1)
EP
Exposed Pad. Thermal pad on the package bottom must be attached to a
heatsinking conduit to improve heat transfer. It is recommended to connect the EP
to the lower potential (VEE).
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage or left
open, and if no signal is applied on Dx, Dx, SEL and SEL then the device will be susceptible to selfoscillation.
2. CML output require 50 W receiver termination resistor to VCC for proper operation.
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