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參數(shù)資料
| 型號： | NB7L72MMNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 2X2 16QFN |
| 標準包裝： | 123 |
| 功能： | 交叉點開關 |
| 電路： | 1 x 2:2 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.3 V ~ 3.6 V |
| 電流 - 電源： | 135mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 管件 |
NB7L72M
http://onsemi.com
5
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
VOUT w 250 mV
VOUT w 200 mV
7.0
8.5
GHz
fDATAMAX Maximum Operating Data Rate (PRBS23)
10
Gbps
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
fin ≤ 8.5 GHz
200
400
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1GHz, Measured at Differential Crosspoint
INn/INn to Qn/Qn
SELn to Qn/Qn
110
150
180
ps
tPLH TC
Propagation Delay Temperature Coefficient
50
Dfs/°C
tSKEW
OutputtoOutput Skew (within device) (Note 13)
DevicetoDevice Skew (tpdmax – tpdmin)
10
20
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 8.5GHz
45
50
55
%
tjitter
RJ – Output Random Jitter (Note 14)
fin v 8.5 GHz
DJ – Deterministic Jitter (Note 15)
v 10 Gbps
0.2
0.5
10
ps RMS
ps pkpk
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
100
1200
mV
tr,, tf
Output Rise/Fall Times @ 1 GHz (20% 80%),
Q, Q
25
30
50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps
(20% 80%).
12.Output voltage swing is a singleended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
16.Input voltage swing is a singleended measurement operating in differential mode.
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
fin, Clock Input Frequency (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
500
450
400
350
300
200
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Q AMP (mV)
Figure 4. Input Structure
50 W
VTn
VCC
INn
250
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