
NB7L32M
http://onsemi.com
2
NC
VEE
VCC
RVCC VCC
VCC
Q
VCC
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L32M
Exposed Pad (EP)
VEE
Figure 1. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open, and if no signal is applied on CLK/CLK input then the
device will be susceptible to selfoscillation.
2
CLK
ECL, CML, LVDS Input
Noninverted differential input. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open and if no signal is applied on CLK/CLK input, then the
device will be susceptible to selfoscillation.
3
CLK
ECL, CML, LVDS Input
Inverted differential input. In the differential configuration when the input termin-
ation pin (VTCLK, VTCLK) are connected to a common termination voltage or
left open and if no signal is applied on CLK/CLK input, then the device will be
susceptible to selfoscillation.
4
VTCLK
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open and if no signal is applied on CLK/CLK input, then the
device will be susceptible to selfoscillation.
5
NC
No connect. NC pin must be left open.
6, 7, 8
VEE
Negative supply voltage.
9, 12, 13,
14, 16
VCC
Positive supply voltage.
10
Q
CML Output
Inverted differential output. Typically terminated with 50 W resistor to VCC.
11
Q
CML Output
Noninverted differential output. Typically terminated with 50 W resistor to VCC.
15
R
LVTTL/LVCMOS
Reset Input. Internal pulldown to 75 kW to VEE.
EP
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a heatsinking conduit. EP is electrically isolated
from VCC and VEE.