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參數(shù)資料
型號(hào): NB7L32MMNG
廠商: ON Semiconductor
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK DIVIDER 1:2 16-QFN
標(biāo)準(zhǔn)包裝: 123
類型: 時(shí)鐘除法器
PLL:
輸入: CML,ECL,LVDS,LVPECL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 14GHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
NB7L32M
http://onsemi.com
2
NC
VEE
VCC
RVCC VCC
VCC
Q
VCC
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L32M
Exposed Pad (EP)
VEE
Figure 1. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open, and if no signal is applied on CLK/CLK input then the
device will be susceptible to selfoscillation.
2
CLK
ECL, CML, LVDS Input
Noninverted differential input. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open and if no signal is applied on CLK/CLK input, then the
device will be susceptible to selfoscillation.
3
CLK
ECL, CML, LVDS Input
Inverted differential input. In the differential configuration when the input termin-
ation pin (VTCLK, VTCLK) are connected to a common termination voltage or
left open and if no signal is applied on CLK/CLK input, then the device will be
susceptible to selfoscillation.
4
VTCLK
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination
voltage or left open and if no signal is applied on CLK/CLK input, then the
device will be susceptible to selfoscillation.
5
NC
No connect. NC pin must be left open.
6, 7, 8
VEE
Negative supply voltage.
9, 12, 13,
14, 16
VCC
Positive supply voltage.
10
Q
CML Output
Inverted differential output. Typically terminated with 50 W resistor to VCC.
11
Q
CML Output
Noninverted differential output. Typically terminated with 50 W resistor to VCC.
15
R
LVTTL/LVCMOS
Reset Input. Internal pulldown to 75 kW to VEE.
EP
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a heatsinking conduit. EP is electrically isolated
from VCC and VEE.
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