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參數(shù)資料
| 型號(hào)： | NB6L295MNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 511TAP 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 92 |
| 標(biāo)片/步級(jí)數(shù)： | 512 |
| 功能： | 多重，可編程 |
| 延遲到第一抽頭： | 3.2ns，6.2ns |
| 接頭增量： | 11ps |
| 可用的總延遲： | 3.2ns ~ 8.5ns，6.2ns ~ 16.6ns |
| 獨(dú)立延遲數(shù)： | 2 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | NB6L295MNG-ND NB6L295MNGOS |
NB6L295
http://onsemi.com
3
SDIN
SLOAD
VCC
VT1
VCC0
Q0
VCC0
VCC1
Q1
VCC1
GND
VT1
VCC
VT0 GND
EN
SCLK
IN0
IN1
IN0
Q1
Q0
VT0
NB6L295
18
12
4
3
5
6
78
9
11
10
2
1
17
16
15
14
13
19
24
23
22
20
21
Exposed Pad
(EP)
Figure 2. Pinout: QFN24 (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VCC
Power Supply
Positive Supply Voltage for the Inputs and Core Logic
2
EN
LVCMOS/LVTTL Input
Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default
state LOW (37 kW pulldown resistor). High forces Q LOW and Q HIGH.
3
SLOAD
LVCMOS/LVTTL Input
Serial Load; This pin loads the configuration latches with the contents of the shift register. The
latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH
toLOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown
resistor).
4
SDIN
LVCMOS/LVTTL Input
Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin
Default state LOW (37 kW pulldown resistor).
5
SCLK
LVCMOS/LVTTL Input
Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is
sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor).
6
VCC
Power Supply
Positive Supply Voltage for the Inputs and Core Logic
7
VT1
Internal 50 W Termination Pin for IN1
8
IN1
LVPECL, CML, LVDS Input
Noninverted differential input. Note 1.
9
IN1
LVPECL, CML, LVDS Input
Inverted differential input. Note 1.
10
VT1
Internal 50 W Termination Pin for IN1
11
GND
Power Supply
Negative Power Supply
12
VCC1
Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
13
Q1
LVPECL Output
Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 2.0 V.
14
Q1
LVPECL Output
Noninverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 2.0 V.
15
VCC1
Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
16
VCC0
Power Supply
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
17
Q0
LVPECL Output
Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to
VCC0 2.0 V.
18
Q0
LVPECL Output
Noninverted Differential Output . Channel 0. Typically terminated with 50 W resistor to
VCC0 2.0 V.
19
VCC0
Power Supply
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
20
GND
Power Supply
Negative Power Supply
21
VT0
Internal 50 W Termination Pin for IN0
22
IN0
LVPECL, CML, LVDS Input
Inverted differential input. Note 1.
23
IN0
LVPECL, CML, LVDS Input
Noninverted differential input. Note 1.
24
VT0
Internal 50 W Termination Pin for IN0
EP
Ground
The Exposed Pad (EP) on the QFN24 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to GND and must be connected to GND on the PC
board.
1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input then the device will be susceptible to selfoscillation.
2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected
to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.
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