參數(shù)資料
型號: NB6L239MN
廠商: ON SEMICONDUCTOR
元件分類: 時鐘及定時
英文描述: 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ±1/2/4/8, ±2/4/8/16 Clock Divider
中文描述: 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16
封裝: 3 X 3 MM, QFN-16
文件頁數(shù): 1/12頁
文件大?。?/td> 94K
代理商: NB6L239MN
Semiconductor Components Industries, LLC, 2004
April, 2004 Rev. 0
1
Publication Order Number:
NB6L239/D
NB6L239
2.5 V / 3.3 V Any Differential
Clock IN to Differential
LVPECL OUT
÷
1/2/4/8,
÷
2/4/8/16 Clock Divider
Features
The NB6L239 is a highspeed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios;
and
2/4/8/16. Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7).
Maximum Clock Input Frequency, 3.0 GHz
Input Compatibility with LVDS/LVPECL/CML/HSTL
Rise/Fall Time 70 ps Typical
< 10 ps Typical OutputtoOutput Skew
Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs
Internal 50 Termination Provided
Random Clock Jitter < 1 ps RMS
Divideby1 Edge of QA Aligned to QB Divided Output
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Master Reset for Synchronization of Multiple Chips
V
BBAC
Reference Output
Synchronous Output Enable/Disable
1/2/4/8
CLK
CLK
EN
Figure 1. Simplified Logic Diagram
QB
QB
MR
QA
QA
SELB1
SELB0
SELA1
SELA0
VT
+
MARKING DIAGRAM*
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
XXXX
XXXX
ALYW
XXXX
A
L
Y
W
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Bottom View
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
相關PDF資料
PDF描述
NB6L72 2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL Outputs(帶LVPECL輸出的2.5V/3.3V差分2 X 2交點開關)
NB6N11S 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator(3.3V 1:2 AnyLevel輸入到LVDS輸出緩沖器/譯碼器)
NB6N239S 3.3V,3.0GHz Any Differential Clock IN to LVDS OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider(3.3V,3.0GHz差分時鐘輸入到LVDS輸出,÷1/2/4/8, ÷2/4/8/16時鐘分頻器)
NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/Translator with CML Outputs and Internal Termination(帶CML輸出和內(nèi)部端口的2.5V/3.3V差分1:2時鐘/數(shù)據(jù)輸出緩沖器/轉(zhuǎn)換器)
NB7L216 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination(帶內(nèi)部端口的2.5V/3.3V,12Gb/s多級時鐘/數(shù)據(jù)輸入到RSECL,高增益接收器/緩沖器/轉(zhuǎn)換器)
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