參數(shù)資料
型號(hào): NB6L14MMNR2G
廠商: ON Semiconductor
文件頁數(shù): 1/10頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER 1:4 3GHZ 16-QFN
標(biāo)準(zhǔn)包裝: 1
系列: ECLinPS MAX™
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 3GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 剪切帶 (CT)
其它名稱: NB6L14MMNR2GOSCT
Semiconductor Components Industries, LLC, 2008
April, 2008 - Rev. 3
1
Publication Order Number:
NB6L14M/D
NB6L14M
2.5 V/3.3 V3.0 GHz
Differential 1:4 CML Fanout
Buffer
Multi-Level Inputs with Internal Termination
Description
The NB6L14M is a 3.0 GHz differential 1:4 CML clock or data
fanout buffer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14M to accept various logic standards, such as
LVPECL, CML, or LVDS logic levels. The 16 mA differential CML
outputs provide matching internal 50
W terminations and produce
400 mV output swings when externally terminated with a 50
W
resistor to VCC. The VREFAC reference output can be used to rebias
capacitor-coupled differential or single-ended input signals. The 1:4
fanout design was optimized for low output skew applications.
The NB6L14M is a member of the ECLinPS MAX
family of high
performance clock and data products.
Features
Input Clock Frequency > 3.0 GHz
Input Data Rate > 2.5 Gb/s
< 20 ps Within Device Output Skew
350 ps Typical Propagation Delay
90 ps Typical Rise and Fall Times
Differential CML Outputs, 340 mV Amplitude, Typical
CML Mode Operating Range: VCC = 2.375 V to 3.63 V with
GND = 0 V
Internal Input and Output Termination Resistors, 50 W
VREFAC Reference Output Voltage
-40°C to +85°C Ambient Operating Temperature
Available in 3 mm x 3 mm 16 Pin QFN
These are Pb-Free Devices
MARKING
DIAGRAM*
http://onsemi.com
QFN-16
MN SUFFIX
CASE 485G
NB6L
14M
ALYW
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
16
1
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
Figure 1. Simplified Logic Diagram
Q
D
Q0
Q1
Q2
Q3
IN
VT
IN
EN
VREFAC
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