參數(shù)資料
型號(hào): NB4N840M
廠商: ON SEMICONDUCTOR
英文描述: 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination(帶CML輸出和內(nèi)部終端的3.3V,2.7Gb/s雙差分時(shí)鐘/數(shù)據(jù)2x2交點(diǎn)開(kāi)關(guān))
中文描述: 3.3 2.7Gb / s雙差分時(shí)鐘/帶CML輸出和內(nèi)部終端(帶白血病輸出和內(nèi)部終端的3.3伏,2.7Gb /數(shù)據(jù)2 × 2交叉點(diǎn)開(kāi)關(guān)S雙差分時(shí)鐘/數(shù)據(jù)2X2的交點(diǎn)開(kāi)關(guān))
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 166K
代理商: NB4N840M
Semiconductor Components Industries, LLC, 2006
May, 2006
Rev. 1
1
Publication Order Number:
NB4N840M/D
NB4N840M
3.3V 2.7Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4N840M is a high
bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET DWDM and high speed switching.
Fully differential design techniques are used to minimize jitter
accumulation, crosstalk, and signal skew, which make this device
ideal for loop
through and protection channel switching applications.
Each 2 x 2 crosspoint switch can fan
out and/or multiplex up to
2.7 Gb/s data and 2.7 GHz clock signals.
Internally terminated differential CML inputs accept AC
coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50
input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 terminations, and 400 mV output swings when
externally terminated, 50 to V
CC
.
Single
ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan
out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32
pin QFN package.
Features
Plug
in compatible to the MAX3840 and SY55859L
Maximum Input Clock Frequency 2.7 GHz
Maximum Input Data Frequency 2.7 Gb/s
225 ps Typical Propagation Delay
80 ps Typical Rise and Fall Times
7 ps Channel to Channel Skew
430 mW Power Consumption
< 0.5 ps RMS Jitter
7 ps Peak
to
Peak Data Dependent Jitter
Power Saving Feature with Disabled Outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
CML Output Level (400 mV Peak
to
Peak Output), Differential
Output
These are Pb
Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB4N
840M
ALYWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
CML
CML
CML
CML
CML
CML
CML
CML
0
1
0
1
0
1
0
1
Figure 1. Functional Block Diagram
QA0
QA0
ENA0
SELA0
QA1
QA1
ENA1
SELA1
QB0
QB0
ENB0
SELB0
QB1
QB1
ENB1
SELB1
DA0
DA0
DA1
DA1
DB0
DB0
DB1
DB1
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