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參數(shù)資料
| 型號(hào)： | NB3N65027DTR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK SYNTHESIZER 3PLL 20QSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:7 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-QSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NB3N65027DTR2GOSDKR |
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 2
1
Publication Order Number:
NB3N65027/D
NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
The NB3N65027 is a LVCMOS PLLsynthesized clock generator.
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phaselocked loops (PLLs).
Control lines ACSx, BCSx and CCS will select their appropriate
bank output frequencies. ACS1 and BCS1 are twolevel
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
threelevel LVCMOS inputs, High, Mid and Low.
The NB3N65027 has three independent LVTTL/LVCMOS output
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
The NB3N65027 operates from a single +3.3 V supply across the
operating temperature range from 40
°C to +85°C, and is offered in a
QSOP20 RoHS compliant package.
The NB3N65027 provides the optimum combination of low cost,
flexibility, and high performance for Network, PCI and SDRAM
applications.
Features
12.5 MHz or 25 MHz Fundamental Crystal or Clock
Input
Six Output Clocks with Selectable Frequencies
Buffered Crystal Reference Output
SDRAM Frequencies of 67, 83, 100, and 133 MHz
LVCMOS with 25 mA Output Drive Capability at TTL
Levels
Operating Range: VCC = 3.3 V ±10%
QSOP20 Package, 150 mil
40°C to +85°C Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
Figure 1. Simplified Logic Diagram
Buffer /
Oscillator
Clock
Synthesis
and Control
Circuitry
25 or 12.5 MHz
crystal or clock
ACS1
CLKA1
GND
X1/ICLK
X2
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT
VDD
OE (all outputs)
ACS0
BCS1
BCS0
B2
CCS
PLLC
PLLB
PLLA
CLX2
CLX1
QSOP20
CASE 492AC
MARKING DIAGRAM
http://onsemi.com
3N65027 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
3N65027
AWLYWWG
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|---|---|
| NB3N853501EDTG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2:1:4 LVPECL FAN-OUT BUFF RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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