參數(shù)資料
型號: NB3N3020DTGEVB
廠商: ON Semiconductor
文件頁數(shù): 3/9頁
文件大小: 0K
描述: BOARD EVAL NB3N3020 CLOCK MULT
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘乘法器
嵌入式:
已用 IC / 零件: NB3N3020
主要屬性: 1 輸入,2 輸出
次要屬性: SMA 連接器
已供物品:
其它名稱: NB3N3020DTGEVB-ND
NB3N3020DTGEVBOS
NB3N3020
http://onsemi.com
3
Table 2. OUTPUT FREQUENCY CLOCK MULTIPLIER SELECT TABLE
Sel2
Sel1
Sel0
CLK1, CLK2, CLK2
Clock Input Range [MHz]
Crystal Input Range [MHz]
L
Low (Power Down)
L
M
Input X 1
25 210
25 27
L
H
Input X 4/3 (or 1 1/3)
15 157.5
15 27
L
M
L
Input X 1.5
10 140
10 27
L
M
1.6
25 – 131.25
25 27
L
M
H
Input X 1.875
40 112
L
H
L
Input X 2
25 105
25 27
L
H
M
Input X 7/3 (or 2 1/3)
15 90
15 27
L
H
Input X 2.4
25 – 87.5
25 27
M
L
Input X 2.5
10 84
10 27
M
L
M
Input X 8/3 (or 2 2/3)
15 78.75
15 27
M
L
H
Input X 3
15 70
15 27
M
L
Input X 3.125
40 – 67.20
M
Input X 3.2
25 – 65.63
25 27
M
H
Input X 10/3 (or 3 1/3)
15 63
15 27
M
H
L
Input X 3.75
20 56
20 27
M
H
M
Input X 4
2 – 52.5
5 25
M
H
Input X 5
6 42
6 27
H
L
Input X 6
5 35
5 27
H
L
M
Input X 6.25
20 – 33.6
20 27
H
L
H
Input X 19/3 (or 6 1/3)
15 – 33.16
15 – 27
H
M
L
Input X 8
5 – 26.25
H
M
Input X 25/3 (or 8 1/3)
15 – 25.2
H
M
H
Input X 10
5 21
H
L
Input X 12
5 – 17.5
H
M
Input X 12.5
10 – 16.8
H
Input X 16
5 13.125
5 – 13.125
L – Low, M – Mid, H High
Recommended Crystal Parameters
Crystal
Fundamental ATCut
Frequency
5 27 MHz
Load Capacitance
16 20 pF
Shunt Capacitance, C0
7 pF Max
Equivalent Series Resistance
35
W Max
Initial Accuracy at 25
°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
C0/C1 Ration
250 Max
Device Operation
The NB3N3020 is a Clock multiplier. The device can take
crystal or clock input and generates LVPECL and
LVCMOS/ LVTTL clock outputs which are multiples of the
input as determined by the trilevel select inputs [Sel0, Sel1,
Sel2].
Clock Multiplication
NB3N3020 is a clock multiplier with the clock multiplier
selected by the tri level select inputs [Sel0, Sel1, Sel2].
NB3N3020 has a LVTTL/LVCMOS output [CLK1] and a
LVPECL clock output [CLK2, CLK2].
Output Enable
The device has an output enable [OE] which is used to
tristate the outputs. OE1 controls the CLK1 clock output
where as OE2 controls the CLK2, CLK2 clock outputs.
When OE1or OE2 are disabled, the respective clock
output(s) are tristated. In this mode of operation, PLL is
still running, with the respective clock outputs tristated.
When the OE1 or OE2 are enabled, the clock outputs
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