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參數(shù)資料
| 型號： | NB3N3002DTR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN XTAL-HCSL 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
NB3N3002
http://onsemi.com
4
Symbol
Characteristic
Min
Typ
Max
Unit
fCLKIN
Clock/Crystal Input Frequency
25
MHz
fCLKOUT
Output Clock Frequency
25
200
MHz
qNOISE
PhaseNoise Performance
fCLK = 200 MHz/100 MHz
dBc/Hz
@ 100 Hz offset from carrier
103/109
@ 1 kHz offset from carrier
118/127.8
@ 10 kHz offset from carrier
122/136.2
@ 100 kHz offset from carrier
130/138.8
@ 1 MHz offset from carrier
138/138.2
@ 10 MHz offset from carrier
149/164
tjit(f)
RMS Phase Jitter (at 125 MHz @ 1 MHz 40 MHz)
0.25
0.50
ps
tjitter (TIE)
TIE RMS Jitter (Note 8)
fCLK = 200 MHz
2.5
ps
CycletoCycle RMS Jitter (Note 9)
fCLK = 200 MHz
2
5
CycletoCycle Peak to Peak Jitter (Note 9)
fCLK = 200 MHz
20
35
Period RMS Jitter (Note 9)
fCLK = 200 MHz
1.5
3
Period PeaktoPeak Jitter (Note 9)
fCLK = 200 MHz
10
20
OE
Output Enable/Disable Time
1.0
ms
tDUTY_CYCLE Output Clock Duty Cycle (Measured at cross point)
45
50
55
%
tR
Output Risetime (Measured from 175 mV to 525 mV, Figure 4)
175
340
700
ps
tF
Output Falltime (Measured from 525 mV to 175 mV, Figure 4)
175
340
700
ps
DtR
Output Risetime Variation (SingleEnded)
125
ps
DtF
Output Falltime Variation (SingleEnded)
125
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. NB3N circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Measurement taken from differential output on singleended channel terminated with RS = 33.2 W, RL = 49.9 W, with load capacitance of
8. Sampled with 20000 cycles to capture jitter component down to 100 kHz.
9. Sampled with 20000 cycles.
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|---|---|
| NB3N3010BDG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 AUDIO OVERSAMPLING RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| NB3N3010BDR2G | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 AUDIO OVERSAMPLING CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| NB3N3011 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V 100 MHz / 106.25 MHz PureEdge Clock Generator with LVPECL Differential Output |
| NB3N3011DTEVB | 功能描述:BOARD EVAL FOR NB3N3011 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| NB3N3011DTG | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 XTAL 3.3V LVPECL CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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