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參數(shù)資料
| 型號(hào)： | NA53 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 英文描述： | NA53 is a 5-input NAND gate with 3x drive strength |
| 中文描述： | NA53是5的3倍驅(qū)動(dòng)強(qiáng)度輸入與非門 |
| 文件頁(yè)數(shù)： | 1/1頁(yè) |
| 文件大小： | 9K |
| 代理商： | NA53 |
NA53 is a 5-input NAND gate with 3x drive strength.
Truth Table
Q
C
D
E
A
B
Capacitance
A
B
C
D
E
Q
Ci (pF)
L
X
X
X
X
H
X
L
X
X
X
H
X
X
L
X
X
H
X
X
X
L
X
H
X
X
X
X
L
H
H
H
H
H
H
L
A
B
C
D
E
0.050
0.050
0.053
0.056
0.056
Area
Power
1.22 mils
2
14.31
μW
/
MHz
Delay [ns] = tpd.. = f(SL, L)
Output Slope [ns] = op_sl.. = f(L)
with SL = Input Slope [ns] ; L = Output Load [pF]
with L = Output Load [pF]
AC Characteristics : Tj = 25°C VDD = 5V Typical Process
AC Characteristics
Characteristics
Symbol
SL = 0.1
SL = 2.0
L = 0.3
L = 2.1
L = 3.0
L = 0.3
L = 2.1
L = 3.0
Delay A to Q
tpdar
tpdaf
tpdbr
tpdbf
tpdcr
tpdcf
tpddr
tpddf
tpder
tpdef
0.57
0.51
0.65
0.56
0.72
0.59
0.78
0.61
0.84
0.61
1.56
1.38
1.64
1.44
1.71
1.45
1.78
1.48
1.83
1.50
2.09
1.82
2.16
1.86
2.24
1.90
2.30
1.95
2.35
1.92
0.91
0.49
1.02
0.52
1.10
0.51
1.19
0.49
1.26
0.44
1.88
1.35
2.01
1.38
2.11
1.38
2.19
1.35
2.25
1.30
2.37
1.80
2.53
1.82
2.58
1.82
2.67
1.79
2.74
1.73
Delay B to Q
Delay C to Q
Delay D to Q
Delay E to Q
Output Slope A to Q
op_slar
op_slaf
op_slbr
op_slbf
0.67
0.55
0.67
0.52
3.93
2.87
3.93
2.90
5.46
4.03
5.48
4.05
0.65
0.53
0.67
0.53
3.90
2.87
3.91
2.91
5.57
3.92
5.55
4.07
Output Slope B to Q
Output Slope C to Q
op_slcr
op_slcf
0.67
0.52
3.95
2.85
5.46
4.01
0.68
0.53
3.92
2.90
5.58
4.08
Output Slope D to Q
op_sldr
op_sldf
0.67
0.53
3.90
2.86
5.57
4.12
0.68
0.53
3.93
2.88
5.52
4.07
Output Slope E to Q
op_sler
op_slef
0.68
0.52
3.88
2.91
5.53
4.05
0.67
0.53
3.93
2.87
5.57
4.07
Rev. N/C
Sept. 1996
- 233 -
Austria Mikro Systeme International
R
0.6 μm CMOS
CUB
NA53
NA53
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